UMC_BASE           53 drivers/gpu/drm/amd/amdgpu/vega20_reg_init.c 		adev->reg_offset[UMC_HWIP][i] = (uint32_t *)(&(UMC_BASE.instance[i]));
UMC_BASE          211 drivers/gpu/drm/amd/include/arct_ip_offset.h static const struct IP_BASE UMC_BASE            ={ { { { 0x000132C0, 0x00014000, 0x00425800, 0, 0, 0 } },
UMC_BASE          127 drivers/gpu/drm/amd/include/navi10_ip_offset.h static const struct IP_BASE UMC_BASE            ={ { { { 0x00014000, 0, 0, 0, 0, 0 } },
UMC_BASE          172 drivers/gpu/drm/amd/include/navi12_ip_offset.h static const struct IP_BASE UMC_BASE ={ { { { 0x00014000, 0x02425800, 0, 0, 0 } },
UMC_BASE          172 drivers/gpu/drm/amd/include/navi14_ip_offset.h static const struct IP_BASE UMC_BASE ={ { { { 0x00014000, 0x02425800, 0, 0, 0 } },
UMC_BASE          207 drivers/gpu/drm/amd/include/renoir_ip_offset.h static const struct IP_BASE UMC_BASE ={ { { { 0x00014000, 0x02425800, 0, 0, 0 } },
UMC_BASE          183 drivers/gpu/drm/amd/include/vega10_ip_offset.h static const struct IP_BASE UMC_BASE			= { { { { 0x00014000, 0, 0, 0, 0 } },
UMC_BASE          135 drivers/gpu/drm/amd/include/vega20_ip_offset.h static const struct IP_BASE UMC_BASE            ={ { { { 0x00014000, 0, 0, 0, 0, 0 } },