umr              4207 drivers/infiniband/hw/mlx5/qp.c static void set_reg_umr_seg(struct mlx5_wqe_umr_ctrl_seg *umr,
umr              4212 drivers/infiniband/hw/mlx5/qp.c 	memset(umr, 0, sizeof(*umr));
umr              4214 drivers/infiniband/hw/mlx5/qp.c 	umr->flags = flags;
umr              4215 drivers/infiniband/hw/mlx5/qp.c 	umr->xlt_octowords = cpu_to_be16(get_xlt_octo(size));
umr              4216 drivers/infiniband/hw/mlx5/qp.c 	umr->mkey_mask = frwr_mkey_mask(atomic);
umr              4219 drivers/infiniband/hw/mlx5/qp.c static void set_linv_umr_seg(struct mlx5_wqe_umr_ctrl_seg *umr)
umr              4221 drivers/infiniband/hw/mlx5/qp.c 	memset(umr, 0, sizeof(*umr));
umr              4222 drivers/infiniband/hw/mlx5/qp.c 	umr->mkey_mask = cpu_to_be64(MLX5_MKEY_MASK_FREE);
umr              4223 drivers/infiniband/hw/mlx5/qp.c 	umr->flags = MLX5_UMR_INLINE;
umr              4291 drivers/infiniband/hw/mlx5/qp.c 			       struct mlx5_wqe_umr_ctrl_seg *umr,
umr              4296 drivers/infiniband/hw/mlx5/qp.c 	memset(umr, 0, sizeof(*umr));
umr              4301 drivers/infiniband/hw/mlx5/qp.c 			umr->flags = MLX5_UMR_CHECK_FREE;
umr              4304 drivers/infiniband/hw/mlx5/qp.c 			umr->flags = MLX5_UMR_CHECK_NOT_FREE;
umr              4307 drivers/infiniband/hw/mlx5/qp.c 	umr->xlt_octowords = cpu_to_be16(get_xlt_octo(umrwr->xlt_size));
umr              4311 drivers/infiniband/hw/mlx5/qp.c 		umr->xlt_offset = cpu_to_be16(offset & 0xffff);
umr              4312 drivers/infiniband/hw/mlx5/qp.c 		umr->xlt_offset_47_16 = cpu_to_be32(offset >> 16);
umr              4313 drivers/infiniband/hw/mlx5/qp.c 		umr->flags |= MLX5_UMR_TRANSLATION_OFFSET_EN;
umr              4316 drivers/infiniband/hw/mlx5/qp.c 		umr->mkey_mask |= get_umr_update_translation_mask();
umr              4318 drivers/infiniband/hw/mlx5/qp.c 		umr->mkey_mask |= get_umr_update_access_mask(atomic);
umr              4319 drivers/infiniband/hw/mlx5/qp.c 		umr->mkey_mask |= get_umr_update_pd_mask();
umr              4322 drivers/infiniband/hw/mlx5/qp.c 		umr->mkey_mask |= get_umr_enable_mr_mask();
umr              4324 drivers/infiniband/hw/mlx5/qp.c 		umr->mkey_mask |= get_umr_disable_mr_mask();
umr              4327 drivers/infiniband/hw/mlx5/qp.c 		umr->flags |= MLX5_UMR_INLINE;
umr              4329 drivers/infiniband/hw/mlx5/qp.c 	return umr_check_mkey_mask(dev, be64_to_cpu(umr->mkey_mask));
umr              4719 drivers/infiniband/hw/mlx5/qp.c static void set_sig_umr_segment(struct mlx5_wqe_umr_ctrl_seg *umr,
umr              4722 drivers/infiniband/hw/mlx5/qp.c 	memset(umr, 0, sizeof(*umr));
umr              4724 drivers/infiniband/hw/mlx5/qp.c 	umr->flags = MLX5_FLAGS_INLINE | MLX5_FLAGS_CHECK_FREE;
umr              4725 drivers/infiniband/hw/mlx5/qp.c 	umr->xlt_octowords = cpu_to_be16(get_xlt_octo(size));
umr              4726 drivers/infiniband/hw/mlx5/qp.c 	umr->bsf_octowords = cpu_to_be16(MLX5_MKEY_BSF_OCTO_SIZE);
umr              4727 drivers/infiniband/hw/mlx5/qp.c 	umr->mkey_mask = sig_mkey_mask();
umr               381 drivers/net/ethernet/mellanox/mlx5/core/en.h 		} umr;
umr               582 drivers/net/ethernet/mellanox/mlx5/core/en.h 	struct mlx5e_umr_dma_info umr;
umr                93 drivers/net/ethernet/mellanox/mlx5/core/en/xsk/rx.c 	struct mlx5e_dma_info *di = &wi->umr.dma_info[page_idx];
umr               438 drivers/net/ethernet/mellanox/mlx5/core/en_rx.c 	struct mlx5e_dma_info *dma_info = wi->umr.dma_info;
umr               488 drivers/net/ethernet/mellanox/mlx5/core/en_rx.c 	struct mlx5e_dma_info *dma_info = &wi->umr.dma_info[0];
umr               530 drivers/net/ethernet/mellanox/mlx5/core/en_rx.c 	sq->db.ico_wqe[pi].umr.rq = rq;
umr               636 drivers/net/ethernet/mellanox/mlx5/core/en_rx.c 				wi->umr.rq->mpwqe.umr_completed++;
umr              1241 drivers/net/ethernet/mellanox/mlx5/core/en_rx.c 	struct mlx5e_dma_info *di = &wi->umr.dma_info[page_idx];
umr              1286 drivers/net/ethernet/mellanox/mlx5/core/en_rx.c 	struct mlx5e_dma_info *di = &wi->umr.dma_info[page_idx];