umc_reg_offset     39 drivers/gpu/drm/amd/amdgpu/amdgpu_umc.h 	uint32_t umc_inst, channel_inst, umc_reg_offset, channel_index;	\
umc_reg_offset     47 drivers/gpu/drm/amd/amdgpu/amdgpu_umc.h 			umc_reg_offset = adev->umc.channel_offs * channel_inst;	\
umc_reg_offset     51 drivers/gpu/drm/amd/amdgpu/amdgpu_umc.h 			(func)(adev, err_data, umc_reg_offset, channel_index);	\
umc_reg_offset     79 drivers/gpu/drm/amd/amdgpu/umc_v6_1.c 						   uint32_t umc_reg_offset,
umc_reg_offset     95 drivers/gpu/drm/amd/amdgpu/umc_v6_1.c 	ecc_err_cnt_sel = RREG32(ecc_err_cnt_sel_addr + umc_reg_offset);
umc_reg_offset     98 drivers/gpu/drm/amd/amdgpu/umc_v6_1.c 	WREG32(ecc_err_cnt_sel_addr + umc_reg_offset, ecc_err_cnt_sel);
umc_reg_offset     99 drivers/gpu/drm/amd/amdgpu/umc_v6_1.c 	ecc_err_cnt = RREG32(ecc_err_cnt_addr + umc_reg_offset);
umc_reg_offset    104 drivers/gpu/drm/amd/amdgpu/umc_v6_1.c 	WREG32(ecc_err_cnt_addr + umc_reg_offset, UMC_V6_1_CE_CNT_INIT);
umc_reg_offset    109 drivers/gpu/drm/amd/amdgpu/umc_v6_1.c 	WREG32(ecc_err_cnt_sel_addr + umc_reg_offset, ecc_err_cnt_sel);
umc_reg_offset    110 drivers/gpu/drm/amd/amdgpu/umc_v6_1.c 	ecc_err_cnt = RREG32(ecc_err_cnt_addr + umc_reg_offset);
umc_reg_offset    115 drivers/gpu/drm/amd/amdgpu/umc_v6_1.c 	WREG32(ecc_err_cnt_addr + umc_reg_offset, UMC_V6_1_CE_CNT_INIT);
umc_reg_offset    119 drivers/gpu/drm/amd/amdgpu/umc_v6_1.c 	mc_umc_status = RREG64_UMC(mc_umc_status_addr + umc_reg_offset);
umc_reg_offset    127 drivers/gpu/drm/amd/amdgpu/umc_v6_1.c 						      uint32_t umc_reg_offset,
umc_reg_offset    137 drivers/gpu/drm/amd/amdgpu/umc_v6_1.c 	mc_umc_status = RREG64_UMC(mc_umc_status_addr + umc_reg_offset);
umc_reg_offset    148 drivers/gpu/drm/amd/amdgpu/umc_v6_1.c 					   struct ras_err_data *err_data, uint32_t umc_reg_offset,
umc_reg_offset    151 drivers/gpu/drm/amd/amdgpu/umc_v6_1.c 	umc_v6_1_query_correctable_error_count(adev, umc_reg_offset,
umc_reg_offset    153 drivers/gpu/drm/amd/amdgpu/umc_v6_1.c 	umc_v6_1_querry_uncorrectable_error_count(adev, umc_reg_offset,
umc_reg_offset    165 drivers/gpu/drm/amd/amdgpu/umc_v6_1.c 					 uint32_t umc_reg_offset, uint32_t channel_index)
umc_reg_offset    176 drivers/gpu/drm/amd/amdgpu/umc_v6_1.c 		WREG64_UMC(mc_umc_status_addr + umc_reg_offset, 0x0ULL);
umc_reg_offset    180 drivers/gpu/drm/amd/amdgpu/umc_v6_1.c 	mc_umc_status = RREG64_UMC(mc_umc_status_addr + umc_reg_offset);
umc_reg_offset    186 drivers/gpu/drm/amd/amdgpu/umc_v6_1.c 		err_addr = RREG64_PCIE(smnMCA_UMC0_MCUMC_ADDRT0 + umc_reg_offset * 4);
umc_reg_offset    203 drivers/gpu/drm/amd/amdgpu/umc_v6_1.c 	WREG64_UMC(mc_umc_status_addr + umc_reg_offset, 0x0ULL);
umc_reg_offset    214 drivers/gpu/drm/amd/amdgpu/umc_v6_1.c 					 uint32_t umc_reg_offset, uint32_t channel_index)
umc_reg_offset    225 drivers/gpu/drm/amd/amdgpu/umc_v6_1.c 	ecc_err_cnt_sel = RREG32(ecc_err_cnt_sel_addr + umc_reg_offset);
umc_reg_offset    231 drivers/gpu/drm/amd/amdgpu/umc_v6_1.c 	WREG32(ecc_err_cnt_sel_addr + umc_reg_offset, ecc_err_cnt_sel);
umc_reg_offset    233 drivers/gpu/drm/amd/amdgpu/umc_v6_1.c 	WREG32(ecc_err_cnt_addr + umc_reg_offset, UMC_V6_1_CE_CNT_INIT);
umc_reg_offset    238 drivers/gpu/drm/amd/amdgpu/umc_v6_1.c 	WREG32(ecc_err_cnt_sel_addr + umc_reg_offset, ecc_err_cnt_sel);
umc_reg_offset    239 drivers/gpu/drm/amd/amdgpu/umc_v6_1.c 	WREG32(ecc_err_cnt_addr + umc_reg_offset, UMC_V6_1_CE_CNT_INIT);