ulv 5098 drivers/gpu/drm/amd/amdgpu/si_dpm.c struct si_ulv_param *ulv = &si_pi->ulv; ulv 5102 drivers/gpu/drm/amd/amdgpu/si_dpm.c ret = si_convert_power_level_to_smc(adev, &ulv->pl, ulv 5111 drivers/gpu/drm/amd/amdgpu/si_dpm.c if (ulv->one_pcie_lane_in_ulv) ulv 5127 drivers/gpu/drm/amd/amdgpu/si_dpm.c struct si_ulv_param *ulv = &si_pi->ulv; ulv 5131 drivers/gpu/drm/amd/amdgpu/si_dpm.c ret = si_populate_memory_timing_parameters(adev, &ulv->pl, ulv 5137 drivers/gpu/drm/amd/amdgpu/si_dpm.c ulv->volt_change_delay); ulv 5161 drivers/gpu/drm/amd/amdgpu/si_dpm.c const struct si_ulv_param *ulv = &si_pi->ulv; ulv 5221 drivers/gpu/drm/amd/amdgpu/si_dpm.c if (ulv->supported && ulv->pl.vddc) { ulv 5230 drivers/gpu/drm/amd/amdgpu/si_dpm.c WREG32(CG_ULV_CONTROL, ulv->cg_ulv_control); ulv 5231 drivers/gpu/drm/amd/amdgpu/si_dpm.c WREG32(CG_ULV_PARAMETER, ulv->cg_ulv_parameter); ulv 5600 drivers/gpu/drm/amd/amdgpu/si_dpm.c struct si_ulv_param *ulv = &si_pi->ulv; ulv 5602 drivers/gpu/drm/amd/amdgpu/si_dpm.c if (ulv->supported) ulv 5613 drivers/gpu/drm/amd/amdgpu/si_dpm.c const struct si_ulv_param *ulv = &si_pi->ulv; ulv 5617 drivers/gpu/drm/amd/amdgpu/si_dpm.c if (state->performance_levels[0].mclk != ulv->pl.mclk) ulv 5625 drivers/gpu/drm/amd/amdgpu/si_dpm.c if (ulv->pl.vddc < ulv 5641 drivers/gpu/drm/amd/amdgpu/si_dpm.c const struct si_ulv_param *ulv = &si_pi->ulv; ulv 5643 drivers/gpu/drm/amd/amdgpu/si_dpm.c if (ulv->supported) { ulv 5757 drivers/gpu/drm/amd/amdgpu/si_dpm.c struct si_ulv_param *ulv = &si_pi->ulv; ulv 5760 drivers/gpu/drm/amd/amdgpu/si_dpm.c if (ulv->supported && ulv->pl.vddc) { ulv 6110 drivers/gpu/drm/amd/amdgpu/si_dpm.c struct si_ulv_param *ulv = &si_pi->ulv; ulv 6127 drivers/gpu/drm/amd/amdgpu/si_dpm.c if (ulv->supported && ulv->pl.vddc != 0) ulv 6128 drivers/gpu/drm/amd/amdgpu/si_dpm.c si_convert_mc_reg_table_entry_to_smc(adev, &ulv->pl, ulv 7174 drivers/gpu/drm/amd/amdgpu/si_dpm.c si_pi->ulv.supported = false; ulv 7175 drivers/gpu/drm/amd/amdgpu/si_dpm.c si_pi->ulv.pl = *pl; ulv 7176 drivers/gpu/drm/amd/amdgpu/si_dpm.c si_pi->ulv.one_pcie_lane_in_ulv = false; ulv 7177 drivers/gpu/drm/amd/amdgpu/si_dpm.c si_pi->ulv.volt_change_delay = SISLANDS_ULVVOLTAGECHANGEDELAY_DFLT; ulv 7178 drivers/gpu/drm/amd/amdgpu/si_dpm.c si_pi->ulv.cg_ulv_parameter = SISLANDS_CGULVPARAMETER_DFLT; ulv 7179 drivers/gpu/drm/amd/amdgpu/si_dpm.c si_pi->ulv.cg_ulv_control = SISLANDS_CGULVCONTROL_DFLT; ulv 671 drivers/gpu/drm/amd/amdgpu/si_dpm.h struct evergreen_ulv_param ulv; ulv 967 drivers/gpu/drm/amd/amdgpu/si_dpm.h struct si_ulv_param ulv; ulv 1391 drivers/gpu/drm/radeon/btc_dpm.c if (eg_pi->ulv.supported) { ulv 1403 drivers/gpu/drm/radeon/btc_dpm.c struct rv7xx_pl *ulv_pl = eg_pi->ulv.pl; ulv 1677 drivers/gpu/drm/radeon/btc_dpm.c if (eg_pi->ulv.supported) { ulv 1680 drivers/gpu/drm/radeon/btc_dpm.c eg_pi->ulv.supported = false; ulv 1788 drivers/gpu/drm/radeon/btc_dpm.c if (eg_pi->ulv.supported) ulv 1797 drivers/gpu/drm/radeon/btc_dpm.c struct rv7xx_pl *ulv_pl = eg_pi->ulv.pl; ulv 1815 drivers/gpu/drm/radeon/btc_dpm.c struct rv7xx_pl *ulv_pl = eg_pi->ulv.pl; ulv 1844 drivers/gpu/drm/radeon/btc_dpm.c if (eg_pi->ulv.supported) { ulv 2568 drivers/gpu/drm/radeon/btc_dpm.c eg_pi->ulv.supported = false; ulv 3108 drivers/gpu/drm/radeon/ci_dpm.c struct ci_ulv_parm *ulv = &pi->ulv; ulv 3110 drivers/gpu/drm/radeon/ci_dpm.c if (ulv->supported) { ulv 3132 drivers/gpu/drm/radeon/ci_dpm.c pi->ulv.supported = false; ulv 3558 drivers/gpu/drm/radeon/ci_dpm.c struct ci_ulv_parm *ulv = &pi->ulv; ulv 3581 drivers/gpu/drm/radeon/ci_dpm.c if (ulv->supported) { ulv 3585 drivers/gpu/drm/radeon/ci_dpm.c WREG32_SMC(CG_ULV_PARAMETER, ulv->cg_ulv_parameter); ulv 5502 drivers/gpu/drm/radeon/ci_dpm.c pi->ulv.supported = true; ulv 5503 drivers/gpu/drm/radeon/ci_dpm.c pi->ulv.pl = *pl; ulv 5504 drivers/gpu/drm/radeon/ci_dpm.c pi->ulv.cg_ulv_parameter = CISLANDS_CGULVPARAMETER_DFLT; ulv 232 drivers/gpu/drm/radeon/ci_dpm.h struct ci_ulv_parm ulv; ulv 2037 drivers/gpu/drm/radeon/cypress_dpm.c eg_pi->ulv.supported = false; ulv 87 drivers/gpu/drm/radeon/cypress_dpm.h struct evergreen_ulv_param ulv; ulv 3956 drivers/gpu/drm/radeon/ni_dpm.c eg_pi->ulv.supported = true; ulv 3957 drivers/gpu/drm/radeon/ni_dpm.c eg_pi->ulv.pl = pl; ulv 4063 drivers/gpu/drm/radeon/ni_dpm.c eg_pi->ulv.supported = false; ulv 2236 drivers/gpu/drm/radeon/rv770_dpm.c eg_pi->ulv.supported = true; ulv 2237 drivers/gpu/drm/radeon/rv770_dpm.c eg_pi->ulv.pl = pl; ulv 4635 drivers/gpu/drm/radeon/si_dpm.c struct si_ulv_param *ulv = &si_pi->ulv; ulv 4639 drivers/gpu/drm/radeon/si_dpm.c ret = si_convert_power_level_to_smc(rdev, &ulv->pl, ulv 4648 drivers/gpu/drm/radeon/si_dpm.c if (ulv->one_pcie_lane_in_ulv) ulv 4664 drivers/gpu/drm/radeon/si_dpm.c struct si_ulv_param *ulv = &si_pi->ulv; ulv 4668 drivers/gpu/drm/radeon/si_dpm.c ret = si_populate_memory_timing_parameters(rdev, &ulv->pl, ulv 4674 drivers/gpu/drm/radeon/si_dpm.c ulv->volt_change_delay); ulv 4699 drivers/gpu/drm/radeon/si_dpm.c const struct si_ulv_param *ulv = &si_pi->ulv; ulv 4759 drivers/gpu/drm/radeon/si_dpm.c if (ulv->supported && ulv->pl.vddc) { ulv 4768 drivers/gpu/drm/radeon/si_dpm.c WREG32(CG_ULV_CONTROL, ulv->cg_ulv_control); ulv 4769 drivers/gpu/drm/radeon/si_dpm.c WREG32(CG_ULV_PARAMETER, ulv->cg_ulv_parameter); ulv 5138 drivers/gpu/drm/radeon/si_dpm.c struct si_ulv_param *ulv = &si_pi->ulv; ulv 5140 drivers/gpu/drm/radeon/si_dpm.c if (ulv->supported) ulv 5151 drivers/gpu/drm/radeon/si_dpm.c const struct si_ulv_param *ulv = &si_pi->ulv; ulv 5155 drivers/gpu/drm/radeon/si_dpm.c if (state->performance_levels[0].mclk != ulv->pl.mclk) ulv 5163 drivers/gpu/drm/radeon/si_dpm.c if (ulv->pl.vddc < ulv 5179 drivers/gpu/drm/radeon/si_dpm.c const struct si_ulv_param *ulv = &si_pi->ulv; ulv 5181 drivers/gpu/drm/radeon/si_dpm.c if (ulv->supported) { ulv 5297 drivers/gpu/drm/radeon/si_dpm.c struct si_ulv_param *ulv = &si_pi->ulv; ulv 5300 drivers/gpu/drm/radeon/si_dpm.c if (ulv->supported && ulv->pl.vddc) { ulv 5656 drivers/gpu/drm/radeon/si_dpm.c struct si_ulv_param *ulv = &si_pi->ulv; ulv 5673 drivers/gpu/drm/radeon/si_dpm.c if (ulv->supported && ulv->pl.vddc != 0) ulv 5674 drivers/gpu/drm/radeon/si_dpm.c si_convert_mc_reg_table_entry_to_smc(rdev, &ulv->pl, ulv 6774 drivers/gpu/drm/radeon/si_dpm.c si_pi->ulv.supported = false; ulv 6775 drivers/gpu/drm/radeon/si_dpm.c si_pi->ulv.pl = *pl; ulv 6776 drivers/gpu/drm/radeon/si_dpm.c si_pi->ulv.one_pcie_lane_in_ulv = false; ulv 6777 drivers/gpu/drm/radeon/si_dpm.c si_pi->ulv.volt_change_delay = SISLANDS_ULVVOLTAGECHANGEDELAY_DFLT; ulv 6778 drivers/gpu/drm/radeon/si_dpm.c si_pi->ulv.cg_ulv_parameter = SISLANDS_CGULVPARAMETER_DFLT; ulv 6779 drivers/gpu/drm/radeon/si_dpm.c si_pi->ulv.cg_ulv_control = SISLANDS_CGULVCONTROL_DFLT; ulv 160 drivers/gpu/drm/radeon/si_dpm.h struct si_ulv_param ulv;