ulptx_memwrite_dsgl  240 drivers/infiniband/hw/cxgb4/mem.c 	if (!rdev->lldi.ulptx_memwrite_dsgl || !use_dsgl) {
ulptx_memwrite_dsgl  708 drivers/infiniband/hw/cxgb4/mem.c 	    max_num_sg > t4_max_fr_depth(rhp->rdev.lldi.ulptx_memwrite_dsgl &&
ulptx_memwrite_dsgl  300 drivers/infiniband/hw/cxgb4/provider.c 		t4_max_fr_depth(dev->rdev.lldi.ulptx_memwrite_dsgl && use_dsgl);
ulptx_memwrite_dsgl 1204 drivers/infiniband/hw/cxgb4/qp.c 				       rhp->rdev.lldi.ulptx_memwrite_dsgl);
ulptx_memwrite_dsgl  400 drivers/net/ethernet/chelsio/cxgb4/cxgb4.h 	bool ulptx_memwrite_dsgl;          /* use of T5 DSGL allowed */
ulptx_memwrite_dsgl 4637 drivers/net/ethernet/chelsio/cxgb4/cxgb4_main.c 		adap->params.ulptx_memwrite_dsgl = false;
ulptx_memwrite_dsgl 4642 drivers/net/ethernet/chelsio/cxgb4/cxgb4_main.c 		adap->params.ulptx_memwrite_dsgl = (ret == 0 && val[0] != 0);
ulptx_memwrite_dsgl  691 drivers/net/ethernet/chelsio/cxgb4/cxgb4_uld.c 	lld->ulptx_memwrite_dsgl = adap->params.ulptx_memwrite_dsgl;
ulptx_memwrite_dsgl  356 drivers/net/ethernet/chelsio/cxgb4/cxgb4_uld.h 	bool ulptx_memwrite_dsgl;            /* use of T5 DSGL allowed */