TxPwrLimit_5G    1772 drivers/staging/rtl8723bs/hal/hal_com_phycfg.c 			limits[i] = hal_data->TxPwrLimit_5G[i]
TxPwrLimit_5G    1780 drivers/staging/rtl8723bs/hal/hal_com_phycfg.c 			hal_data->TxPwrLimit_5G[idx_regulation]
TxPwrLimit_5G    1824 drivers/staging/rtl8723bs/hal/hal_com_phycfg.c 					tempPwrLmt = pHalData->TxPwrLimit_5G[regulation][bw][rateSection][channel][ODM_RF_PATH_A];
TxPwrLimit_5G    1856 drivers/staging/rtl8723bs/hal/hal_com_phycfg.c 								pHalData->TxPwrLimit_5G[regulation][bw][baseSection][channel][ODM_RF_PATH_A] =
TxPwrLimit_5G    1857 drivers/staging/rtl8723bs/hal/hal_com_phycfg.c 									pHalData->TxPwrLimit_5G[regulation][bw][refSection][channel][ODM_RF_PATH_A];
TxPwrLimit_5G    1937 drivers/staging/rtl8723bs/hal/hal_com_phycfg.c 						pHalData->TxPwrLimit_5G[i][j][k][m][l] = MAX_POWER_INDEX;
TxPwrLimit_5G    2030 drivers/staging/rtl8723bs/hal/hal_com_phycfg.c 		prevPowerLimit = pHalData->TxPwrLimit_5G[regulation][bandwidth][rateSection][channelIndex][ODM_RF_PATH_A];
TxPwrLimit_5G    2033 drivers/staging/rtl8723bs/hal/hal_com_phycfg.c 			pHalData->TxPwrLimit_5G[regulation][bandwidth][rateSection][channelIndex][ODM_RF_PATH_A] = powerLimit;
TxPwrLimit_5G     289 drivers/staging/rtl8723bs/include/hal_data.h 	s8	TxPwrLimit_5G[MAX_REGULATION_NUM]