TxPwrLimit_2_4G  1754 drivers/staging/rtl8723bs/hal/hal_com_phycfg.c 			limits[i] = hal_data->TxPwrLimit_2_4G[i]
TxPwrLimit_2_4G  1762 drivers/staging/rtl8723bs/hal/hal_com_phycfg.c 			hal_data->TxPwrLimit_2_4G[idx_regulation]
TxPwrLimit_2_4G  1885 drivers/staging/rtl8723bs/hal/hal_com_phycfg.c 					tempPwrLmt = pHalData->TxPwrLimit_2_4G[regulation][bw][rateSection][channel][ODM_RF_PATH_A];
TxPwrLimit_2_4G  1906 drivers/staging/rtl8723bs/hal/hal_com_phycfg.c 							pHalData->TxPwrLimit_2_4G[regulation][bw][rateSection][channel][rfPath] = tempValue;
TxPwrLimit_2_4G  1929 drivers/staging/rtl8723bs/hal/hal_com_phycfg.c 						pHalData->TxPwrLimit_2_4G[i][j][k][m][l] = MAX_POWER_INDEX;
TxPwrLimit_2_4G  2017 drivers/staging/rtl8723bs/hal/hal_com_phycfg.c 		prevPowerLimit = pHalData->TxPwrLimit_2_4G[regulation][bandwidth][rateSection][channelIndex][ODM_RF_PATH_A];
TxPwrLimit_2_4G  2020 drivers/staging/rtl8723bs/hal/hal_com_phycfg.c 			pHalData->TxPwrLimit_2_4G[regulation][bandwidth][rateSection][channelIndex][ODM_RF_PATH_A] = powerLimit;
TxPwrLimit_2_4G   282 drivers/staging/rtl8723bs/include/hal_data.h 	s8	TxPwrLimit_2_4G[MAX_REGULATION_NUM]