uclk_states 3160 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c struct pp_smu_nv_clock_table *max_clocks, unsigned int *uclk_states, unsigned int num_states) uclk_states 3182 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c calculated_states[i].dram_speed_mts = uclk_states[i] * 16 / 1000; uclk_states 3185 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c min_fclk_required_by_uclk = mul_u64_u32_shr(BIT_ULL(32) * 1080 / 1000000, uclk_states[i], 32); uclk_states 3395 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c unsigned int uclk_states[8] = {0}; uclk_states 3403 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c (&pool->base.pp_smu->nv_funcs.pp_smu, uclk_states, &num_states); uclk_states 3419 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c update_bounding_box(dc, loaded_bb, &max_clocks, uclk_states, num_states);