uc_pll_ref_div    397 drivers/gpu/drm/amd/powerplay/hwmgr/ppatomctrl.c 		dividers->uc_pll_ref_div =
uc_pll_ref_div    467 drivers/gpu/drm/amd/powerplay/hwmgr/ppatomctrl.c 		dividers->uc_pll_ref_div =
uc_pll_ref_div     88 drivers/gpu/drm/amd/powerplay/hwmgr/ppatomctrl.h 	uint8_t   uc_pll_ref_div;                      /* Output Parameter: PLL ref divider */
uc_pll_ref_div     98 drivers/gpu/drm/amd/powerplay/hwmgr/ppatomctrl.h 	uint8_t   uc_pll_ref_div;                      /*Output Parameter: PLL ref divider */
uc_pll_ref_div    319 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 	ref_divider = 1 + dividers.uc_pll_ref_div;
uc_pll_ref_div    326 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 			SPLL_REF_DIV, dividers.uc_pll_ref_div);
uc_pll_ref_div    881 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 	ref_divider = 1 + dividers.uc_pll_ref_div;
uc_pll_ref_div    888 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 			SPLL_REF_DIV, dividers.uc_pll_ref_div);
uc_pll_ref_div    819 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c 	reference_divider = 1 + dividers.uc_pll_ref_div;
uc_pll_ref_div    826 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c 		CG_SPLL_FUNC_CNTL, SPLL_REF_DIV, dividers.uc_pll_ref_div);
uc_pll_ref_div    562 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 	reference_divider = 1 + dividers.uc_pll_ref_div;
uc_pll_ref_div    569 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 		CG_SPLL_FUNC_CNTL, SPLL_REF_DIV, dividers.uc_pll_ref_div);