uc_pll_post_div   399 drivers/gpu/drm/amd/powerplay/hwmgr/ppatomctrl.c 		dividers->uc_pll_post_div =
uc_pll_post_div   469 drivers/gpu/drm/amd/powerplay/hwmgr/ppatomctrl.c 		dividers->uc_pll_post_div =
uc_pll_post_div    89 drivers/gpu/drm/amd/powerplay/hwmgr/ppatomctrl.h 	uint8_t   uc_pll_post_div;                      /* Output Parameter: PLL post divider */
uc_pll_post_div    99 drivers/gpu/drm/amd/powerplay/hwmgr/ppatomctrl.h 	uint8_t   uc_pll_post_div;                     /*Output Parameter: PLL post divider */
uc_pll_post_div   328 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 			SPLL_PDIV_A,  dividers.uc_pll_post_div);
uc_pll_post_div   341 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 		uint32_t vco_freq = clock * dividers.uc_pll_post_div;
uc_pll_post_div   890 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 			SPLL_PDIV_A,  dividers.uc_pll_post_div);
uc_pll_post_div   904 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 		uint32_t vco_freq = clock * dividers.uc_pll_post_div;
uc_pll_post_div   828 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c 		CG_SPLL_FUNC_CNTL, SPLL_PDIV_A,  dividers.uc_pll_post_div);
uc_pll_post_div   842 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c 		uint32_t vcoFreq = engine_clock * dividers.uc_pll_post_div;
uc_pll_post_div   571 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 		CG_SPLL_FUNC_CNTL, SPLL_PDIV_A,  dividers.uc_pll_post_div);
uc_pll_post_div   585 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 		uint32_t vcoFreq = engine_clock * dividers.uc_pll_post_div;