uasm_i_mtc0       233 arch/mips/include/asm/uasm.h # define UASM_i_MTC0(buf, rt, rd...) uasm_i_mtc0(buf, rt, rd)
uasm_i_mtc0       283 arch/mips/kernel/pm-cps.c 	uasm_i_mtc0(pp, t0, 25, (perf_counter * 2) + 0); /* PerfCtlN */
uasm_i_mtc0       285 arch/mips/kernel/pm-cps.c 	uasm_i_mtc0(pp, zero, 25, (perf_counter * 2) + 1); /* PerfCntN */
uasm_i_mtc0       321 arch/mips/kernel/pm-cps.c 	uasm_i_mtc0(pp, t2, 25, (perf_counter * 2) + 0); /* PerfCtlN */
uasm_i_mtc0       323 arch/mips/kernel/pm-cps.c 	uasm_i_mtc0(pp, t3, 25, (perf_counter * 2) + 1); /* PerfCntN */
uasm_i_mtc0       442 arch/mips/kernel/pm-cps.c 				uasm_i_mtc0(&p, t0, 2, 4);
uasm_i_mtc0       196 arch/mips/kvm/entry.c 		uasm_i_mtc0(p, reg, C0_EBASE);
uasm_i_mtc0       259 arch/mips/kvm/entry.c 	uasm_i_mtc0(&p, K0, C0_STATUS);
uasm_i_mtc0       274 arch/mips/kvm/entry.c 	uasm_i_mtc0(&p, K0, C0_STATUS);
uasm_i_mtc0       336 arch/mips/kvm/entry.c 	uasm_i_mtc0(&p, K0, C0_GUESTCTL0);
uasm_i_mtc0       351 arch/mips/kvm/entry.c 		uasm_i_mtc0(&p, T0, C0_GUESTCTL1);
uasm_i_mtc0       418 arch/mips/kvm/entry.c 	 uasm_i_mtc0(&p, K0, C0_ENTRYHI);
uasm_i_mtc0       421 arch/mips/kvm/entry.c 	uasm_i_mtc0(&p, K0, C0_ENTRYHI);
uasm_i_mtc0       427 arch/mips/kvm/entry.c 	uasm_i_mtc0(&p, ZERO, C0_HWRENA);
uasm_i_mtc0       671 arch/mips/kvm/entry.c 	uasm_i_mtc0(&p, K0, C0_STATUS);
uasm_i_mtc0       737 arch/mips/kvm/entry.c 	uasm_i_mtc0(&p, K0, C0_GUESTCTL0);
uasm_i_mtc0       752 arch/mips/kvm/entry.c 		uasm_i_mtc0(&p, T0, C0_GUESTCTL1);
uasm_i_mtc0       764 arch/mips/kvm/entry.c 	uasm_i_mtc0(&p, V0, C0_STATUS);
uasm_i_mtc0       787 arch/mips/kvm/entry.c 	uasm_i_mtc0(&p, K0, C0_HWRENA);
uasm_i_mtc0       882 arch/mips/kvm/entry.c 	uasm_i_mtc0(&p, K0, C0_STATUS);
uasm_i_mtc0       890 arch/mips/kvm/entry.c 	uasm_i_mtc0(&p, V1, C0_STATUS);
uasm_i_mtc0       934 arch/mips/kvm/entry.c 	uasm_i_mtc0(&p, K0, C0_HWRENA);
uasm_i_mtc0       431 arch/mips/mm/tlbex.c 	uasm_i_mtc0(&p, K0, C0_ENTRYLO0);
uasm_i_mtc0       667 arch/mips/mm/tlbex.c 			uasm_i_mtc0(p, tmp, C0_PAGEMASK);
uasm_i_mtc0       671 arch/mips/mm/tlbex.c 			uasm_i_mtc0(p, tmp, C0_PAGEMASK);
uasm_i_mtc0       674 arch/mips/mm/tlbex.c 			uasm_i_mtc0(p, 0, C0_PAGEMASK);
uasm_i_mtc0       687 arch/mips/mm/tlbex.c 			uasm_i_mtc0(p, tmp, C0_PAGEMASK);
uasm_i_mtc0       691 arch/mips/mm/tlbex.c 			uasm_i_mtc0(p, tmp, C0_PAGEMASK);
uasm_i_mtc0       694 arch/mips/mm/tlbex.c 			uasm_i_mtc0(p, 0, C0_PAGEMASK);
uasm_i_mtc0       708 arch/mips/mm/tlbex.c 	uasm_i_mtc0(p, tmp, C0_PAGEMASK);
uasm_i_mtc0      1563 arch/mips/mm/tlbex.c 		uasm_i_mtc0(&p, K0, C0_PAGEMASK);
uasm_i_mtc0      1566 arch/mips/mm/tlbex.c 		uasm_i_mtc0(&p, K0, C0_PAGEMASK);
uasm_i_mtc0      1568 arch/mips/mm/tlbex.c 		uasm_i_mtc0(&p, 0, C0_PAGEMASK);
uasm_i_mtc0      1881 arch/mips/mm/tlbex.c 	uasm_i_mtc0(p, pte, C0_ENTRYLO0); /* cp0 delay */
uasm_i_mtc0      1900 arch/mips/mm/tlbex.c 	uasm_i_mtc0(p, pte, C0_ENTRYLO0); /* cp0 delay */