uasm_i_mfc0       232 arch/mips/include/asm/uasm.h # define UASM_i_MFC0(buf, rt, rd...) uasm_i_mfc0(buf, rt, rd)
uasm_i_mfc0       278 arch/mips/kernel/pm-cps.c 	uasm_i_mfc0(pp, t2, 25, (perf_counter * 2) + 0); /* PerfCtlN */
uasm_i_mfc0       279 arch/mips/kernel/pm-cps.c 	uasm_i_mfc0(pp, t3, 25, (perf_counter * 2) + 1); /* PerfCntN */
uasm_i_mfc0       314 arch/mips/kernel/pm-cps.c 	uasm_i_mfc0(pp, t1, 25, (perf_counter * 2) + 1); /* PerfCntN */
uasm_i_mfc0       233 arch/mips/kvm/entry.c 	uasm_i_mfc0(&p, V0, C0_STATUS);
uasm_i_mfc0       334 arch/mips/kvm/entry.c 	uasm_i_mfc0(&p, K0, C0_GUESTCTL0);
uasm_i_mfc0       345 arch/mips/kvm/entry.c 		uasm_i_mfc0(&p, T0, C0_GUESTCTL1);
uasm_i_mfc0       647 arch/mips/kvm/entry.c 	uasm_i_mfc0(&p, K0, C0_CAUSE);
uasm_i_mfc0       651 arch/mips/kvm/entry.c 		uasm_i_mfc0(&p, K0, C0_BADINSTR);
uasm_i_mfc0       657 arch/mips/kvm/entry.c 		uasm_i_mfc0(&p, K0, C0_BADINSTRP);
uasm_i_mfc0       666 arch/mips/kvm/entry.c 	uasm_i_mfc0(&p, V0, C0_STATUS);
uasm_i_mfc0       699 arch/mips/kvm/entry.c 		uasm_i_mfc0(&p, T0, C0_CONFIG5);
uasm_i_mfc0       735 arch/mips/kvm/entry.c 	uasm_i_mfc0(&p, K0, C0_GUESTCTL0);
uasm_i_mfc0       748 arch/mips/kvm/entry.c 		uasm_i_mfc0(&p, T0, C0_GUESTCTL1);
uasm_i_mfc0       879 arch/mips/kvm/entry.c 	uasm_i_mfc0(&p, V1, C0_STATUS);
uasm_i_mfc0       419 arch/mips/mm/tlbex.c 	uasm_i_mfc0(&p, K0, C0_BADVADDR);
uasm_i_mfc0       425 arch/mips/mm/tlbex.c 	uasm_i_mfc0(&p, K0, C0_CONTEXT);
uasm_i_mfc0       432 arch/mips/mm/tlbex.c 	uasm_i_mfc0(&p, K1, C0_EPC); /* cp0 delay */
uasm_i_mfc0       971 arch/mips/mm/tlbex.c 		uasm_i_mfc0(p, ptr, c0_kscratch(), pgd_reg);
uasm_i_mfc0       972 arch/mips/mm/tlbex.c 		uasm_i_mfc0(p, tmp, C0_BADVADDR); /* get faulting address */
uasm_i_mfc0       978 arch/mips/mm/tlbex.c 		uasm_i_mfc0(p, ptr, SMP_CPUID_REG);
uasm_i_mfc0       985 arch/mips/mm/tlbex.c 		uasm_i_mfc0(p, tmp, C0_BADVADDR); /* get faulting address */
uasm_i_mfc0      1092 arch/mips/mm/tlbex.c 		uasm_i_mfc0(p, tmp, C0_INDEX);
uasm_i_mfc0      1882 arch/mips/mm/tlbex.c 	uasm_i_mfc0(p, tmp, C0_EPC); /* cp0 delay */
uasm_i_mfc0      1899 arch/mips/mm/tlbex.c 	uasm_i_mfc0(p, tmp, C0_INDEX);
uasm_i_mfc0      1902 arch/mips/mm/tlbex.c 	uasm_i_mfc0(p, tmp, C0_EPC); /* branch delay */
uasm_i_mfc0      1918 arch/mips/mm/tlbex.c 	uasm_i_mfc0(p, pte, C0_BADVADDR);
uasm_i_mfc0      1924 arch/mips/mm/tlbex.c 	uasm_i_mfc0(p, pte, C0_CONTEXT);
uasm_i_mfc0      2082 arch/mips/mm/tlbex.c 			uasm_i_mfc0(p, wr.r3, C0_INDEX);