uart_parent_names  128 drivers/clk/mmp/clk-of-mmp2.c static const char *uart_parent_names[] = {"uart_pll", "vctcxo"};
uart_parent_names  142 drivers/clk/mmp/clk-of-mmp2.c 	{0, "uart0_mux", uart_parent_names, ARRAY_SIZE(uart_parent_names), CLK_SET_RATE_PARENT, APBC_UART0, 4, 3, 0, &uart0_lock},
uart_parent_names  143 drivers/clk/mmp/clk-of-mmp2.c 	{0, "uart1_mux", uart_parent_names, ARRAY_SIZE(uart_parent_names), CLK_SET_RATE_PARENT, APBC_UART1, 4, 3, 0, &uart1_lock},
uart_parent_names  144 drivers/clk/mmp/clk-of-mmp2.c 	{0, "uart2_mux", uart_parent_names, ARRAY_SIZE(uart_parent_names), CLK_SET_RATE_PARENT, APBC_UART2, 4, 3, 0, &uart2_lock},
uart_parent_names  145 drivers/clk/mmp/clk-of-mmp2.c 	{0, "uart3_mux", uart_parent_names, ARRAY_SIZE(uart_parent_names), CLK_SET_RATE_PARENT, APBC_UART3, 4, 3, 0, &uart2_lock},
uart_parent_names  116 drivers/clk/mmp/clk-of-pxa168.c static const char *uart_parent_names[] = {"pll1_3_16", "uart_pll"};
uart_parent_names  131 drivers/clk/mmp/clk-of-pxa168.c 	{0, "uart0_mux", uart_parent_names, ARRAY_SIZE(uart_parent_names), CLK_SET_RATE_PARENT, APBC_UART0, 4, 3, 0, &uart0_lock},
uart_parent_names  132 drivers/clk/mmp/clk-of-pxa168.c 	{0, "uart1_mux", uart_parent_names, ARRAY_SIZE(uart_parent_names), CLK_SET_RATE_PARENT, APBC_UART1, 4, 3, 0, &uart1_lock},
uart_parent_names  133 drivers/clk/mmp/clk-of-pxa168.c 	{0, "uart2_mux", uart_parent_names, ARRAY_SIZE(uart_parent_names), CLK_SET_RATE_PARENT, APBC_UART2, 4, 3, 0, &uart2_lock},
uart_parent_names   91 drivers/clk/mmp/clk-of-pxa1928.c static const char *uart_parent_names[] = {"uart_pll", "vctcxo"};
uart_parent_names  100 drivers/clk/mmp/clk-of-pxa1928.c 	{0, "uart0_mux", uart_parent_names, ARRAY_SIZE(uart_parent_names), CLK_SET_RATE_PARENT, PXA1928_CLK_UART0 * 4, 4, 3, 0, &uart0_lock},
uart_parent_names  101 drivers/clk/mmp/clk-of-pxa1928.c 	{0, "uart1_mux", uart_parent_names, ARRAY_SIZE(uart_parent_names), CLK_SET_RATE_PARENT, PXA1928_CLK_UART1 * 4, 4, 3, 0, &uart1_lock},
uart_parent_names  102 drivers/clk/mmp/clk-of-pxa1928.c 	{0, "uart2_mux", uart_parent_names, ARRAY_SIZE(uart_parent_names), CLK_SET_RATE_PARENT, PXA1928_CLK_UART2 * 4, 4, 3, 0, &uart2_lock},
uart_parent_names  103 drivers/clk/mmp/clk-of-pxa1928.c 	{0, "uart3_mux", uart_parent_names, ARRAY_SIZE(uart_parent_names), CLK_SET_RATE_PARENT, PXA1928_CLK_UART3 * 4, 4, 3, 0, &uart3_lock},
uart_parent_names  116 drivers/clk/mmp/clk-of-pxa910.c static const char *uart_parent_names[] = {"pll1_3_16", "uart_pll"};
uart_parent_names  129 drivers/clk/mmp/clk-of-pxa910.c 	{0, "uart0_mux", uart_parent_names, ARRAY_SIZE(uart_parent_names), CLK_SET_RATE_PARENT, APBC_UART0, 4, 3, 0, &uart0_lock},
uart_parent_names  130 drivers/clk/mmp/clk-of-pxa910.c 	{0, "uart1_mux", uart_parent_names, ARRAY_SIZE(uart_parent_names), CLK_SET_RATE_PARENT, APBC_UART1, 4, 3, 0, &uart1_lock},
uart_parent_names  138 drivers/clk/mmp/clk-of-pxa910.c 	{0, "uart2_mux", uart_parent_names, ARRAY_SIZE(uart_parent_names), CLK_SET_RATE_PARENT, APBCP_UART2, 4, 3, 0, &uart2_lock},