uart_ck_sel_parents  870 drivers/clk/mediatek/clk-mt2701.c static const char * const uart_ck_sel_parents[] = {
uart_ck_sel_parents  876 drivers/clk/mediatek/clk-mt2701.c 	MUX(CLK_PERI_UART0_SEL, "uart0_ck_sel", uart_ck_sel_parents,
uart_ck_sel_parents  878 drivers/clk/mediatek/clk-mt2701.c 	MUX(CLK_PERI_UART1_SEL, "uart1_ck_sel", uart_ck_sel_parents,
uart_ck_sel_parents  880 drivers/clk/mediatek/clk-mt2701.c 	MUX(CLK_PERI_UART2_SEL, "uart2_ck_sel", uart_ck_sel_parents,
uart_ck_sel_parents  882 drivers/clk/mediatek/clk-mt2701.c 	MUX(CLK_PERI_UART3_SEL, "uart3_ck_sel", uart_ck_sel_parents,
uart_ck_sel_parents  504 drivers/clk/mediatek/clk-mt8135.c static const char * const uart_ck_sel_parents[] __initconst = {
uart_ck_sel_parents  510 drivers/clk/mediatek/clk-mt8135.c 	MUX(CLK_PERI_UART0_SEL, "uart0_ck_sel", uart_ck_sel_parents, 0x40c, 0, 1),
uart_ck_sel_parents  511 drivers/clk/mediatek/clk-mt8135.c 	MUX(CLK_PERI_UART1_SEL, "uart1_ck_sel", uart_ck_sel_parents, 0x40c, 1, 1),
uart_ck_sel_parents  512 drivers/clk/mediatek/clk-mt8135.c 	MUX(CLK_PERI_UART2_SEL, "uart2_ck_sel", uart_ck_sel_parents, 0x40c, 2, 1),
uart_ck_sel_parents  513 drivers/clk/mediatek/clk-mt8135.c 	MUX(CLK_PERI_UART3_SEL, "uart3_ck_sel", uart_ck_sel_parents, 0x40c, 3, 1),
uart_ck_sel_parents  719 drivers/clk/mediatek/clk-mt8173.c static const char * const uart_ck_sel_parents[] __initconst = {
uart_ck_sel_parents  725 drivers/clk/mediatek/clk-mt8173.c 	MUX(CLK_PERI_UART0_SEL, "uart0_ck_sel", uart_ck_sel_parents, 0x40c, 0, 1),
uart_ck_sel_parents  726 drivers/clk/mediatek/clk-mt8173.c 	MUX(CLK_PERI_UART1_SEL, "uart1_ck_sel", uart_ck_sel_parents, 0x40c, 1, 1),
uart_ck_sel_parents  727 drivers/clk/mediatek/clk-mt8173.c 	MUX(CLK_PERI_UART2_SEL, "uart2_ck_sel", uart_ck_sel_parents, 0x40c, 2, 1),
uart_ck_sel_parents  728 drivers/clk/mediatek/clk-mt8173.c 	MUX(CLK_PERI_UART3_SEL, "uart3_ck_sel", uart_ck_sel_parents, 0x40c, 3, 1),