CM_MEM_PWR_CTRL   109 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h 	SRI(CM_MEM_PWR_CTRL, CM, id), \
CM_MEM_PWR_CTRL   140 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h 	SRI(CM_MEM_PWR_CTRL, CM, id), \
CM_MEM_PWR_CTRL  1135 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h 	uint32_t CM_MEM_PWR_CTRL; \
CM_MEM_PWR_CTRL   343 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c 	REG_SET(CM_MEM_PWR_CTRL, 0,
CM_MEM_PWR_CTRL   597 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c 	REG_SET(CM_MEM_PWR_CTRL, 0,
CM_MEM_PWR_CTRL   783 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c 	REG_SET(CM_MEM_PWR_CTRL, 0, SHARED_MEM_PWR_DIS, 1);
CM_MEM_PWR_CTRL   817 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c 	REG_SET(CM_MEM_PWR_CTRL, 0, SHARED_MEM_PWR_DIS, 0);
CM_MEM_PWR_CTRL    81 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.c 	REG_UPDATE(CM_MEM_PWR_CTRL, SHARED_MEM_PWR_DIS, power_on == true ? 1:0);
CM_MEM_PWR_CTRL   164 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp_cm.c 	REG_SET(CM_MEM_PWR_CTRL, 0,