uart2_lock 127 drivers/clk/mmp/clk-of-mmp2.c static DEFINE_SPINLOCK(uart2_lock); uart2_lock 144 drivers/clk/mmp/clk-of-mmp2.c {0, "uart2_mux", uart_parent_names, ARRAY_SIZE(uart_parent_names), CLK_SET_RATE_PARENT, APBC_UART2, 4, 3, 0, &uart2_lock}, uart2_lock 145 drivers/clk/mmp/clk-of-mmp2.c {0, "uart3_mux", uart_parent_names, ARRAY_SIZE(uart_parent_names), CLK_SET_RATE_PARENT, APBC_UART3, 4, 3, 0, &uart2_lock}, uart2_lock 170 drivers/clk/mmp/clk-of-mmp2.c {MMP2_CLK_UART2, "uart2_clk", "uart2_mux", CLK_SET_RATE_PARENT, APBC_UART2, 0x7, 0x3, 0x0, 0, &uart2_lock}, uart2_lock 171 drivers/clk/mmp/clk-of-mmp2.c {MMP2_CLK_UART3, "uart3_clk", "uart3_mux", CLK_SET_RATE_PARENT, APBC_UART3, 0x7, 0x3, 0x0, 0, &uart2_lock}, uart2_lock 115 drivers/clk/mmp/clk-of-pxa168.c static DEFINE_SPINLOCK(uart2_lock); uart2_lock 133 drivers/clk/mmp/clk-of-pxa168.c {0, "uart2_mux", uart_parent_names, ARRAY_SIZE(uart_parent_names), CLK_SET_RATE_PARENT, APBC_UART2, 4, 3, 0, &uart2_lock}, uart2_lock 155 drivers/clk/mmp/clk-of-pxa168.c {PXA168_CLK_UART2, "uart2_clk", "uart2_mux", CLK_SET_RATE_PARENT, APBC_UART2, 0x3, 0x3, 0x0, 0, &uart2_lock}, uart2_lock 89 drivers/clk/mmp/clk-of-pxa1928.c static DEFINE_SPINLOCK(uart2_lock); uart2_lock 102 drivers/clk/mmp/clk-of-pxa1928.c {0, "uart2_mux", uart_parent_names, ARRAY_SIZE(uart_parent_names), CLK_SET_RATE_PARENT, PXA1928_CLK_UART2 * 4, 4, 3, 0, &uart2_lock}, uart2_lock 125 drivers/clk/mmp/clk-of-pxa1928.c {PXA1928_CLK_UART2, "uart2_clk", "uart2_mux", CLK_SET_RATE_PARENT, PXA1928_CLK_UART2 * 4, 0x3, 0x3, 0x0, 0, &uart2_lock}, uart2_lock 115 drivers/clk/mmp/clk-of-pxa910.c static DEFINE_SPINLOCK(uart2_lock); uart2_lock 138 drivers/clk/mmp/clk-of-pxa910.c {0, "uart2_mux", uart_parent_names, ARRAY_SIZE(uart_parent_names), CLK_SET_RATE_PARENT, APBCP_UART2, 4, 3, 0, &uart2_lock}, uart2_lock 162 drivers/clk/mmp/clk-of-pxa910.c {PXA910_CLK_UART2, "uart2_clk", "uart2_mux", CLK_SET_RATE_PARENT, APBCP_UART2, 0x3, 0x3, 0x0, 0, &uart2_lock},