uart1_lock 126 drivers/clk/mmp/clk-of-mmp2.c static DEFINE_SPINLOCK(uart1_lock); uart1_lock 143 drivers/clk/mmp/clk-of-mmp2.c {0, "uart1_mux", uart_parent_names, ARRAY_SIZE(uart_parent_names), CLK_SET_RATE_PARENT, APBC_UART1, 4, 3, 0, &uart1_lock}, uart1_lock 169 drivers/clk/mmp/clk-of-mmp2.c {MMP2_CLK_UART1, "uart1_clk", "uart1_mux", CLK_SET_RATE_PARENT, APBC_UART1, 0x7, 0x3, 0x0, 0, &uart1_lock}, uart1_lock 114 drivers/clk/mmp/clk-of-pxa168.c static DEFINE_SPINLOCK(uart1_lock); uart1_lock 132 drivers/clk/mmp/clk-of-pxa168.c {0, "uart1_mux", uart_parent_names, ARRAY_SIZE(uart_parent_names), CLK_SET_RATE_PARENT, APBC_UART1, 4, 3, 0, &uart1_lock}, uart1_lock 154 drivers/clk/mmp/clk-of-pxa168.c {PXA168_CLK_UART1, "uart1_clk", "uart1_mux", CLK_SET_RATE_PARENT, APBC_UART1, 0x3, 0x3, 0x0, 0, &uart1_lock}, uart1_lock 88 drivers/clk/mmp/clk-of-pxa1928.c static DEFINE_SPINLOCK(uart1_lock); uart1_lock 101 drivers/clk/mmp/clk-of-pxa1928.c {0, "uart1_mux", uart_parent_names, ARRAY_SIZE(uart_parent_names), CLK_SET_RATE_PARENT, PXA1928_CLK_UART1 * 4, 4, 3, 0, &uart1_lock}, uart1_lock 124 drivers/clk/mmp/clk-of-pxa1928.c {PXA1928_CLK_UART1, "uart1_clk", "uart1_mux", CLK_SET_RATE_PARENT, PXA1928_CLK_UART1 * 4, 0x3, 0x3, 0x0, 0, &uart1_lock}, uart1_lock 114 drivers/clk/mmp/clk-of-pxa910.c static DEFINE_SPINLOCK(uart1_lock); uart1_lock 130 drivers/clk/mmp/clk-of-pxa910.c {0, "uart1_mux", uart_parent_names, ARRAY_SIZE(uart_parent_names), CLK_SET_RATE_PARENT, APBC_UART1, 4, 3, 0, &uart1_lock}, uart1_lock 152 drivers/clk/mmp/clk-of-pxa910.c {PXA910_CLK_UART1, "uart1_clk", "uart1_mux", CLK_SET_RATE_PARENT, APBC_UART1, 0x3, 0x3, 0x0, 0, &uart1_lock},