uart0_parents      73 drivers/clk/mediatek/clk-mt8516.c static const char * const uart0_parents[] __initconst = {
uart0_parents     363 drivers/clk/mediatek/clk-mt8516.c 	MUX(CLK_TOP_UART0_SEL, "uart0_sel", uart0_parents,
uart0_parents     360 drivers/clk/spear/spear1310_clock.c static const char *uart0_parents[] = { "pll5_clk", "uart_syn_gclk", };
uart0_parents     559 drivers/clk/spear/spear1310_clock.c 	clk = clk_register_mux(NULL, "uart0_mclk", uart0_parents,
uart0_parents     560 drivers/clk/spear/spear1310_clock.c 			ARRAY_SIZE(uart0_parents),
uart0_parents     421 drivers/clk/spear/spear1340_clock.c static const char *uart0_parents[] = { "pll5_clk", "osc_24m_clk",
uart0_parents     638 drivers/clk/spear/spear1340_clock.c 	clk = clk_register_mux(NULL, "uart0_mclk", uart0_parents,
uart0_parents     639 drivers/clk/spear/spear1340_clock.c 			ARRAY_SIZE(uart0_parents),
uart0_parents     130 drivers/clk/spear/spear3xx_clock.c static const char *uart0_parents[] = { "pll3_clk", "uart_syn_gclk", };
uart0_parents     442 drivers/clk/spear/spear3xx_clock.c 	clk = clk_register_mux(NULL, "uart0_mclk", uart0_parents,
uart0_parents     443 drivers/clk/spear/spear3xx_clock.c 			ARRAY_SIZE(uart0_parents),