uart0_lock        125 drivers/clk/mmp/clk-of-mmp2.c static DEFINE_SPINLOCK(uart0_lock);
uart0_lock        142 drivers/clk/mmp/clk-of-mmp2.c 	{0, "uart0_mux", uart_parent_names, ARRAY_SIZE(uart_parent_names), CLK_SET_RATE_PARENT, APBC_UART0, 4, 3, 0, &uart0_lock},
uart0_lock        168 drivers/clk/mmp/clk-of-mmp2.c 	{MMP2_CLK_UART0, "uart0_clk", "uart0_mux", CLK_SET_RATE_PARENT, APBC_UART0, 0x7, 0x3, 0x0, 0, &uart0_lock},
uart0_lock        113 drivers/clk/mmp/clk-of-pxa168.c static DEFINE_SPINLOCK(uart0_lock);
uart0_lock        131 drivers/clk/mmp/clk-of-pxa168.c 	{0, "uart0_mux", uart_parent_names, ARRAY_SIZE(uart_parent_names), CLK_SET_RATE_PARENT, APBC_UART0, 4, 3, 0, &uart0_lock},
uart0_lock        153 drivers/clk/mmp/clk-of-pxa168.c 	{PXA168_CLK_UART0, "uart0_clk", "uart0_mux", CLK_SET_RATE_PARENT, APBC_UART0, 0x3, 0x3, 0x0, 0, &uart0_lock},
uart0_lock         87 drivers/clk/mmp/clk-of-pxa1928.c static DEFINE_SPINLOCK(uart0_lock);
uart0_lock        100 drivers/clk/mmp/clk-of-pxa1928.c 	{0, "uart0_mux", uart_parent_names, ARRAY_SIZE(uart_parent_names), CLK_SET_RATE_PARENT, PXA1928_CLK_UART0 * 4, 4, 3, 0, &uart0_lock},
uart0_lock        123 drivers/clk/mmp/clk-of-pxa1928.c 	{PXA1928_CLK_UART0, "uart0_clk", "uart0_mux", CLK_SET_RATE_PARENT, PXA1928_CLK_UART0 * 4, 0x3, 0x3, 0x0, 0, &uart0_lock},
uart0_lock        113 drivers/clk/mmp/clk-of-pxa910.c static DEFINE_SPINLOCK(uart0_lock);
uart0_lock        129 drivers/clk/mmp/clk-of-pxa910.c 	{0, "uart0_mux", uart_parent_names, ARRAY_SIZE(uart_parent_names), CLK_SET_RATE_PARENT, APBC_UART0, 4, 3, 0, &uart0_lock},
uart0_lock        151 drivers/clk/mmp/clk-of-pxa910.c 	{PXA910_CLK_UART0, "uart0_clk", "uart0_mux", CLK_SET_RATE_PARENT, APBC_UART0, 0x3, 0x3, 0x0, 0, &uart0_lock},