CM_IGAM_LUT_RW_CONTROL  174 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h 	SRI(CM_IGAM_LUT_RW_CONTROL, CM, id), \
CM_IGAM_LUT_RW_CONTROL 1325 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h 	uint32_t CM_IGAM_LUT_RW_CONTROL; \
CM_IGAM_LUT_RW_CONTROL  656 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c 	REG_GET(CM_IGAM_LUT_RW_CONTROL, CM_IGAM_DGAM_CONFIG_STATUS,
CM_IGAM_LUT_RW_CONTROL  678 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c 	REG_UPDATE(CM_IGAM_LUT_RW_CONTROL, CM_IGAM_LUT_HOST_EN, 0);
CM_IGAM_LUT_RW_CONTROL  750 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c 	REG_GET(CM_IGAM_LUT_RW_CONTROL, CM_IGAM_DGAM_CONFIG_STATUS,
CM_IGAM_LUT_RW_CONTROL  788 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c 		REG_UPDATE(CM_IGAM_LUT_RW_CONTROL, CM_IGAM_LUT_SEL, 0);
CM_IGAM_LUT_RW_CONTROL  790 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c 		REG_UPDATE(CM_IGAM_LUT_RW_CONTROL, CM_IGAM_LUT_SEL, 1);
CM_IGAM_LUT_RW_CONTROL  792 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c 	REG_UPDATE(CM_IGAM_LUT_RW_CONTROL, CM_IGAM_LUT_RW_MODE, 0);
CM_IGAM_LUT_RW_CONTROL  796 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c 	REG_UPDATE(CM_IGAM_LUT_RW_CONTROL, CM_IGAM_LUT_WRITE_EN_MASK, 7);