CM_IGAM_CONTROL   101 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c 	REG_GET(CM_IGAM_CONTROL,
CM_IGAM_CONTROL   103 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c 	REG_GET(CM_IGAM_CONTROL,
CM_IGAM_CONTROL   280 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c 		REG_UPDATE(CM_IGAM_CONTROL, CM_IGAM_INPUT_FORMAT, 3);
CM_IGAM_CONTROL   281 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c 		REG_UPDATE(CM_IGAM_CONTROL, CM_IGAM_LUT_MODE, 1);
CM_IGAM_CONTROL   283 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c 		REG_UPDATE(CM_IGAM_CONTROL, CM_IGAM_INPUT_FORMAT, 2);
CM_IGAM_CONTROL   284 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c 		REG_UPDATE(CM_IGAM_CONTROL, CM_IGAM_LUT_MODE, 0);
CM_IGAM_CONTROL   173 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h 	SRI(CM_IGAM_CONTROL, CM, id), \
CM_IGAM_CONTROL  1324 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h 	uint32_t CM_IGAM_CONTROL; \
CM_IGAM_CONTROL   794 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c 	REG_UPDATE(CM_IGAM_CONTROL, CM_IGAM_INPUT_FORMAT, 0);
CM_IGAM_CONTROL   799 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c 		CM_IGAM_CONTROL,
CM_IGAM_CONTROL   819 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c 	REG_UPDATE(CM_IGAM_CONTROL, CM_IGAM_LUT_MODE, rama_occupied ? 3 : 2);
CM_IGAM_CONTROL   820 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c 	REG_GET(CM_IGAM_CONTROL, CM_IGAM_LUT_MODE, &ram_num);