CM_ICSC_CONTROL    78 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h 	SRI(CM_ICSC_CONTROL, CM, id), \
CM_ICSC_CONTROL  1285 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h 	uint32_t CM_ICSC_CONTROL; \
CM_ICSC_CONTROL   453 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c 		REG_SET(CM_ICSC_CONTROL, 0, CM_ICSC_MODE, 0);
CM_ICSC_CONTROL   509 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c 	REG_SET(CM_ICSC_CONTROL, 0,