Tcpu             1386 arch/arm/mach-sa1100/include/mach/SA-1100.h #define MDCNFG_PrChrg(Tcpu)     	/*  Pre-Charge time [2..32 Tcpu]   */ \
Tcpu             1387 arch/arm/mach-sa1100/include/mach/SA-1100.h                 	(((Tcpu) - 2)/2 << FShft (MDCNFG_TRP))
Tcpu             1388 arch/arm/mach-sa1100/include/mach/SA-1100.h #define MDCNFG_CeilPrChrg(Tcpu) 	/*  Ceil. of PrChrg [2..32 Tcpu]   */ \
Tcpu             1389 arch/arm/mach-sa1100/include/mach/SA-1100.h                 	(((Tcpu) - 1)/2 << FShft (MDCNFG_TRP))
Tcpu             1391 arch/arm/mach-sa1100/include/mach/SA-1100.h #define MDCNFG_Ref(Tcpu)        	/*  Refresh time [2..32 Tcpu]      */ \
Tcpu             1392 arch/arm/mach-sa1100/include/mach/SA-1100.h                 	(((Tcpu) - 2)/2 << FShft (MDCNFG_TRASR))
Tcpu             1393 arch/arm/mach-sa1100/include/mach/SA-1100.h #define MDCNFG_CeilRef(Tcpu)    	/*  Ceil. of Ref [2..32 Tcpu]      */ \
Tcpu             1394 arch/arm/mach-sa1100/include/mach/SA-1100.h                 	(((Tcpu) - 1)/2 << FShft (MDCNFG_TRASR))
Tcpu             1396 arch/arm/mach-sa1100/include/mach/SA-1100.h #define MDCNFG_DataLtch(Tcpu)   	/*  Data Latch delay [0..3 Tcpu]   */ \
Tcpu             1397 arch/arm/mach-sa1100/include/mach/SA-1100.h                 	((Tcpu) << FShft (MDCNFG_TDL))
Tcpu             1400 arch/arm/mach-sa1100/include/mach/SA-1100.h #define MDCNFG_RefInt(Tcpu)     	/*  min. Refresh Interval          */ \
Tcpu             1402 arch/arm/mach-sa1100/include/mach/SA-1100.h                 	((Tcpu)/8 << FShft (MDCNFG_DRI))
Tcpu             1468 arch/arm/mach-sa1100/include/mach/SA-1100.h #define MSC_1stRdAcc(Tcpu)      	/*  1st Read Access time (burst    */ \
Tcpu             1470 arch/arm/mach-sa1100/include/mach/SA-1100.h                 	((((Tcpu) - 3)/2) << FShft (MSC_RDF))
Tcpu             1471 arch/arm/mach-sa1100/include/mach/SA-1100.h #define MSC_Ceil1stRdAcc(Tcpu)  	/*  Ceil. of 1stRdAcc [3..65 Tcpu] */ \
Tcpu             1472 arch/arm/mach-sa1100/include/mach/SA-1100.h                 	((((Tcpu) - 2)/2) << FShft (MSC_RDF))
Tcpu             1473 arch/arm/mach-sa1100/include/mach/SA-1100.h #define MSC_RdAcc(Tcpu)	        	/*  Read Access time (non-burst    */ \
Tcpu             1475 arch/arm/mach-sa1100/include/mach/SA-1100.h                 	((((Tcpu) - 2)/2) << FShft (MSC_RDF))
Tcpu             1476 arch/arm/mach-sa1100/include/mach/SA-1100.h #define MSC_CeilRdAcc(Tcpu)     	/*  Ceil. of RdAcc [2..64 Tcpu]    */ \
Tcpu             1477 arch/arm/mach-sa1100/include/mach/SA-1100.h                 	((((Tcpu) - 1)/2) << FShft (MSC_RDF))
Tcpu             1480 arch/arm/mach-sa1100/include/mach/SA-1100.h #define MSC_NxtRdAcc(Tcpu)      	/*  Next Read Access time (burst   */ \
Tcpu             1482 arch/arm/mach-sa1100/include/mach/SA-1100.h                 	((((Tcpu) - 2)/2) << FShft (MSC_RDN))
Tcpu             1483 arch/arm/mach-sa1100/include/mach/SA-1100.h #define MSC_CeilNxtRdAcc(Tcpu)  	/*  Ceil. of NxtRdAcc [2..64 Tcpu] */ \
Tcpu             1484 arch/arm/mach-sa1100/include/mach/SA-1100.h                 	((((Tcpu) - 1)/2) << FShft (MSC_RDN))
Tcpu             1485 arch/arm/mach-sa1100/include/mach/SA-1100.h #define MSC_WrAcc(Tcpu)	        	/*  Write Access time (non-burst   */ \
Tcpu             1487 arch/arm/mach-sa1100/include/mach/SA-1100.h                 	((((Tcpu) - 2)/2) << FShft (MSC_RDN))
Tcpu             1488 arch/arm/mach-sa1100/include/mach/SA-1100.h #define MSC_CeilWrAcc(Tcpu)     	/*  Ceil. of WrAcc [2..64 Tcpu]    */ \
Tcpu             1489 arch/arm/mach-sa1100/include/mach/SA-1100.h                 	((((Tcpu) - 1)/2) << FShft (MSC_RDN))
Tcpu             1492 arch/arm/mach-sa1100/include/mach/SA-1100.h #define MSC_Rec(Tcpu)	        	/*  Recovery time [0..28 Tcpu]     */ \
Tcpu             1493 arch/arm/mach-sa1100/include/mach/SA-1100.h                 	(((Tcpu)/4) << FShft (MSC_RRR))
Tcpu             1494 arch/arm/mach-sa1100/include/mach/SA-1100.h #define MSC_CeilRec(Tcpu)       	/*  Ceil. of Rec [0..28 Tcpu]      */ \
Tcpu             1495 arch/arm/mach-sa1100/include/mach/SA-1100.h                 	((((Tcpu) + 3)/4) << FShft (MSC_RRR))
Tcpu             1521 arch/arm/mach-sa1100/include/mach/SA-1100.h #define MECR_IOClk(Tcpu)        	/*  I/O Clock [2..64 Tcpu]         */ \
Tcpu             1522 arch/arm/mach-sa1100/include/mach/SA-1100.h                 	((((Tcpu) - 2)/2) << FShft (MECR_BSIO))
Tcpu             1523 arch/arm/mach-sa1100/include/mach/SA-1100.h #define MECR_CeilIOClk(Tcpu)    	/*  Ceil. of IOClk [2..64 Tcpu]    */ \
Tcpu             1524 arch/arm/mach-sa1100/include/mach/SA-1100.h                 	((((Tcpu) - 1)/2) << FShft (MECR_BSIO))
Tcpu             1527 arch/arm/mach-sa1100/include/mach/SA-1100.h #define MECR_AttrClk(Tcpu)      	/*  Attribute Clock [2..64 Tcpu]   */ \
Tcpu             1528 arch/arm/mach-sa1100/include/mach/SA-1100.h                 	((((Tcpu) - 2)/2) << FShft (MECR_BSA))
Tcpu             1529 arch/arm/mach-sa1100/include/mach/SA-1100.h #define MECR_CeilAttrClk(Tcpu)  	/*  Ceil. of AttrClk [2..64 Tcpu]  */ \
Tcpu             1530 arch/arm/mach-sa1100/include/mach/SA-1100.h                 	((((Tcpu) - 1)/2) << FShft (MECR_BSA))
Tcpu             1532 arch/arm/mach-sa1100/include/mach/SA-1100.h #define MECR_MemClk(Tcpu)       	/*  Memory Clock [2..64 Tcpu]      */ \
Tcpu             1533 arch/arm/mach-sa1100/include/mach/SA-1100.h                 	((((Tcpu) - 2)/2) << FShft (MECR_BSM))
Tcpu             1534 arch/arm/mach-sa1100/include/mach/SA-1100.h #define MECR_CeilMemClk(Tcpu)   	/*  Ceil. of MemClk [2..64 Tcpu]   */ \
Tcpu             1535 arch/arm/mach-sa1100/include/mach/SA-1100.h                 	((((Tcpu) - 1)/2) << FShft (MECR_BSM))
Tcpu             1687 arch/arm/mach-sa1100/include/mach/SA-1100.h #define LCCR0_DMADel(Tcpu)      	/*  palette DMA request Delay      */ \
Tcpu             1689 arch/arm/mach-sa1100/include/mach/SA-1100.h                 	((Tcpu)/2 << FShft (LCCR0_PDD))