tx_lx_tx_emp_post1_lvl   64 drivers/gpu/drm/msm/hdmi/hdmi_phy_8996.c 	u32 tx_lx_tx_emp_post1_lvl[HDMI_NUM_TX_CHANNEL];
tx_lx_tx_emp_post1_lvl  326 drivers/gpu/drm/msm/hdmi/hdmi_phy_8996.c 		cfg->tx_lx_tx_emp_post1_lvl[0] =
tx_lx_tx_emp_post1_lvl  327 drivers/gpu/drm/msm/hdmi/hdmi_phy_8996.c 			cfg->tx_lx_tx_emp_post1_lvl[1] =
tx_lx_tx_emp_post1_lvl  328 drivers/gpu/drm/msm/hdmi/hdmi_phy_8996.c 			cfg->tx_lx_tx_emp_post1_lvl[2] = 0x23;
tx_lx_tx_emp_post1_lvl  329 drivers/gpu/drm/msm/hdmi/hdmi_phy_8996.c 		cfg->tx_lx_tx_emp_post1_lvl[3] = 0x27;
tx_lx_tx_emp_post1_lvl  344 drivers/gpu/drm/msm/hdmi/hdmi_phy_8996.c 			cfg->tx_lx_tx_emp_post1_lvl[i] = 0x23;
tx_lx_tx_emp_post1_lvl  355 drivers/gpu/drm/msm/hdmi/hdmi_phy_8996.c 			cfg->tx_lx_tx_emp_post1_lvl[i] = 0x20;
tx_lx_tx_emp_post1_lvl  387 drivers/gpu/drm/msm/hdmi/hdmi_phy_8996.c 		    cfg->tx_lx_tx_emp_post1_lvl[i]);
tx_lx_tx_emp_post1_lvl  507 drivers/gpu/drm/msm/hdmi/hdmi_phy_8996.c 				   cfg.tx_lx_tx_emp_post1_lvl[i]);