tx_ctrl 165 arch/mips/include/asm/sgi/hpc3.h volatile u32 tx_ctrl; /* control register */ tx_ctrl 149 arch/mips/sgi-ip22/ip28-berr.c hpc3.ethtx.ctrl = hpc3c0->ethregs.tx_ctrl; /* HPC3_ETXCTRL_ACTIVE ? */ tx_ctrl 1292 drivers/net/ethernet/alteon/acenic.c set_aceaddr(&info->tx_ctrl.rngptr, TX_RING_BASE); tx_ctrl 1297 drivers/net/ethernet/alteon/acenic.c set_aceaddr(&info->tx_ctrl.rngptr, ap->tx_ring_dma); tx_ctrl 1300 drivers/net/ethernet/alteon/acenic.c info->tx_ctrl.max_len = ACE_TX_RING_ENTRIES(ap); tx_ctrl 1311 drivers/net/ethernet/alteon/acenic.c info->tx_ctrl.flags = tmp; tx_ctrl 580 drivers/net/ethernet/alteon/acenic.h struct ring_ctrl tx_ctrl; tx_ctrl 1102 drivers/net/ethernet/atheros/alx/hw.c hw->stats.tx_ctrl += alx_read_mem32(hw, ALX_MIB_TX_CTRL); tx_ctrl 425 drivers/net/ethernet/atheros/alx/hw.h u64 tx_ctrl; /* TX control frames, excluding pause frames */ tx_ctrl 332 drivers/net/ethernet/atheros/atl1c/atl1c.h unsigned long tx_ctrl; /* The number of packets transmitted is a control frame, excluding Pause frame. */ tx_ctrl 279 drivers/net/ethernet/atheros/atl1e/atl1e.h unsigned long tx_ctrl; /* The number of packets transmitted is a control frame, excluding Pause frame. */ tx_ctrl 342 drivers/net/ethernet/atheros/atlx/atl1.h u32 tx_ctrl; /* TX control frames, excluding pause frames */ tx_ctrl 154 drivers/net/ethernet/hisilicon/hns/hns_dsaf_gmac.c u32 tx_ctrl; tx_ctrl 157 drivers/net/ethernet/hisilicon/hns/hns_dsaf_gmac.c tx_ctrl = dsaf_read_dev(drv, GMAC_TRANSMIT_CONTROL_REG); tx_ctrl 158 drivers/net/ethernet/hisilicon/hns/hns_dsaf_gmac.c dsaf_set_bit(tx_ctrl, GMAC_TX_PAD_EN_B, !!newval); tx_ctrl 159 drivers/net/ethernet/hisilicon/hns/hns_dsaf_gmac.c dsaf_set_bit(tx_ctrl, GMAC_TX_CRC_ADD_B, !!newval); tx_ctrl 160 drivers/net/ethernet/hisilicon/hns/hns_dsaf_gmac.c dsaf_write_dev(drv, GMAC_TRANSMIT_CONTROL_REG, tx_ctrl); tx_ctrl 210 drivers/net/ethernet/hisilicon/hns/hns_dsaf_gmac.c u32 tx_ctrl; tx_ctrl 217 drivers/net/ethernet/hisilicon/hns/hns_dsaf_gmac.c tx_ctrl = dsaf_read_dev(drv, GMAC_TRANSMIT_CONTROL_REG); tx_ctrl 228 drivers/net/ethernet/hisilicon/hns/hns_dsaf_gmac.c port_mode->pad_enable = dsaf_get_bit(tx_ctrl, GMAC_TX_PAD_EN_B); tx_ctrl 229 drivers/net/ethernet/hisilicon/hns/hns_dsaf_gmac.c port_mode->crc_add = dsaf_get_bit(tx_ctrl, GMAC_TX_CRC_ADD_B); tx_ctrl 230 drivers/net/ethernet/hisilicon/hns/hns_dsaf_gmac.c port_mode->an_enable = dsaf_get_bit(tx_ctrl, GMAC_TX_AN_EN_B); tx_ctrl 296 drivers/net/ethernet/hisilicon/hns/hns_dsaf_mac.h u64 tx_ctrl; /* only for xgmac */ tx_ctrl 43 drivers/net/ethernet/hisilicon/hns/hns_dsaf_xgmac.c {"xgmac_tx_mac_ctrol_frame", MAC_STATS_FIELD_OFF(tx_ctrl)}, tx_ctrl 355 drivers/net/ethernet/hisilicon/hns/hns_dsaf_xgmac.c hw_stats->tx_ctrl = hns_mac_reg_read64(drv, XGMAC_TX_MACCTRLPKTS); tx_ctrl 1578 drivers/net/ethernet/nvidia/forcedeth.c u32 tx_ctrl = readl(base + NvRegTransmitterControl); tx_ctrl 1580 drivers/net/ethernet/nvidia/forcedeth.c tx_ctrl |= NVREG_XMITCTL_START; tx_ctrl 1582 drivers/net/ethernet/nvidia/forcedeth.c tx_ctrl &= ~NVREG_XMITCTL_TX_PATH_EN; tx_ctrl 1583 drivers/net/ethernet/nvidia/forcedeth.c writel(tx_ctrl, base + NvRegTransmitterControl); tx_ctrl 1591 drivers/net/ethernet/nvidia/forcedeth.c u32 tx_ctrl = readl(base + NvRegTransmitterControl); tx_ctrl 1594 drivers/net/ethernet/nvidia/forcedeth.c tx_ctrl &= ~NVREG_XMITCTL_START; tx_ctrl 1596 drivers/net/ethernet/nvidia/forcedeth.c tx_ctrl |= NVREG_XMITCTL_TX_PATH_EN; tx_ctrl 1597 drivers/net/ethernet/nvidia/forcedeth.c writel(tx_ctrl, base + NvRegTransmitterControl); tx_ctrl 5342 drivers/net/ethernet/nvidia/forcedeth.c u32 tx_ctrl, mgmt_sema; tx_ctrl 5355 drivers/net/ethernet/nvidia/forcedeth.c tx_ctrl = readl(base + NvRegTransmitterControl); tx_ctrl 5356 drivers/net/ethernet/nvidia/forcedeth.c tx_ctrl |= NVREG_XMITCTL_HOST_SEMA_ACQ; tx_ctrl 5357 drivers/net/ethernet/nvidia/forcedeth.c writel(tx_ctrl, base + NvRegTransmitterControl); tx_ctrl 5360 drivers/net/ethernet/nvidia/forcedeth.c tx_ctrl = readl(base + NvRegTransmitterControl); tx_ctrl 5361 drivers/net/ethernet/nvidia/forcedeth.c if (((tx_ctrl & NVREG_XMITCTL_HOST_SEMA_MASK) == NVREG_XMITCTL_HOST_SEMA_ACQ) && tx_ctrl 5362 drivers/net/ethernet/nvidia/forcedeth.c ((tx_ctrl & NVREG_XMITCTL_MGMT_SEMA_MASK) == NVREG_XMITCTL_MGMT_SEMA_FREE)) { tx_ctrl 5376 drivers/net/ethernet/nvidia/forcedeth.c u32 tx_ctrl; tx_ctrl 5380 drivers/net/ethernet/nvidia/forcedeth.c tx_ctrl = readl(base + NvRegTransmitterControl); tx_ctrl 5381 drivers/net/ethernet/nvidia/forcedeth.c tx_ctrl &= ~NVREG_XMITCTL_HOST_SEMA_ACQ; tx_ctrl 5382 drivers/net/ethernet/nvidia/forcedeth.c writel(tx_ctrl, base + NvRegTransmitterControl); tx_ctrl 246 drivers/net/ethernet/qualcomm/emac/emac.h u64 tx_ctrl; /* control packets other than pause frame */ tx_ctrl 135 drivers/net/ethernet/seeq/sgiseeq.c hregs->rx_ctrl = hregs->tx_ctrl = 0; tx_ctrl 280 drivers/net/ethernet/seeq/sgiseeq.c hregs->tx_cbptr, hregs->tx_ndptr, hregs->tx_ctrl); tx_ctrl 447 drivers/net/ethernet/seeq/sgiseeq.c hregs->tx_ctrl = HPC3_ETXCTRL_ACTIVE; tx_ctrl 456 drivers/net/ethernet/seeq/sgiseeq.c unsigned long status = hregs->tx_ctrl; tx_ctrl 481 drivers/net/ethernet/seeq/sgiseeq.c hregs->tx_ctrl = HPC3_ETXCTRL_ACTIVE; tx_ctrl 638 drivers/net/ethernet/seeq/sgiseeq.c if (!(hregs->tx_ctrl & HPC3_ETXCTRL_ACTIVE)) tx_ctrl 776 drivers/net/ethernet/socionext/netsec.c const struct netsec_tx_pkt_ctrl *tx_ctrl, tx_ctrl 790 drivers/net/ethernet/socionext/netsec.c (tx_ctrl->cksum_offload_flag << NETSEC_TX_SHIFT_CO) | tx_ctrl 791 drivers/net/ethernet/socionext/netsec.c (tx_ctrl->tcp_seg_offload_flag << NETSEC_TX_SHIFT_SO) | tx_ctrl 798 drivers/net/ethernet/socionext/netsec.c de->buf_len_info = (tx_ctrl->tcp_seg_len << 16) | desc->len; tx_ctrl 819 drivers/net/ethernet/socionext/netsec.c struct netsec_tx_pkt_ctrl tx_ctrl = {}; tx_ctrl 861 drivers/net/ethernet/socionext/netsec.c netsec_set_tx_de(priv, tx_ring, &tx_ctrl, &tx_desc, xdpf); tx_ctrl 1116 drivers/net/ethernet/socionext/netsec.c struct netsec_tx_pkt_ctrl tx_ctrl = {}; tx_ctrl 1131 drivers/net/ethernet/socionext/netsec.c tx_ctrl.cksum_offload_flag = true; tx_ctrl 1150 drivers/net/ethernet/socionext/netsec.c tx_ctrl.tcp_seg_offload_flag = true; tx_ctrl 1151 drivers/net/ethernet/socionext/netsec.c tx_ctrl.tcp_seg_len = tso_seg_len; tx_ctrl 1171 drivers/net/ethernet/socionext/netsec.c netsec_set_tx_de(priv, dring, &tx_ctrl, &tx_desc, skb); tx_ctrl 601 drivers/net/hippi/rrunner.c rrpriv->info->tx_ctrl.entry_size = sizeof(struct tx_desc); tx_ctrl 602 drivers/net/hippi/rrunner.c rrpriv->info->tx_ctrl.entries = TX_RING_ENTRIES; tx_ctrl 603 drivers/net/hippi/rrunner.c rrpriv->info->tx_ctrl.mode = 0; tx_ctrl 604 drivers/net/hippi/rrunner.c rrpriv->info->tx_ctrl.pi = 0; tx_ctrl 605 drivers/net/hippi/rrunner.c set_rraddr(&rrpriv->info->tx_ctrl.rngptr, rrpriv->tx_ring_dma); tx_ctrl 1087 drivers/net/hippi/rrunner.c (((rrpriv->info->tx_ctrl.pi + 1) % TX_RING_ENTRIES) tx_ctrl 1272 drivers/net/hippi/rrunner.c rrpriv->info->tx_ctrl.pi); tx_ctrl 1360 drivers/net/hippi/rrunner.c rrpriv->info->tx_ctrl.entries = 0; tx_ctrl 1428 drivers/net/hippi/rrunner.c txctrl = &rrpriv->info->tx_ctrl; tx_ctrl 788 drivers/net/hippi/rrunner.h struct ring_ctrl tx_ctrl; tx_ctrl 515 drivers/net/wireless/ti/wlcore/acx.h __le32 tx_ctrl;