tx_base_offset    217 drivers/soc/fsl/qe/ucc_slow.c 	uccs->tx_base_offset =
tx_base_offset    220 drivers/soc/fsl/qe/ucc_slow.c 	if (IS_ERR_VALUE(uccs->tx_base_offset)) {
tx_base_offset    222 drivers/soc/fsl/qe/ucc_slow.c 		uccs->tx_base_offset = 0;
tx_base_offset    228 drivers/soc/fsl/qe/ucc_slow.c 	bd = uccs->confBd = uccs->tx_bd = qe_muram_addr(uccs->tx_base_offset);
tx_base_offset    296 drivers/soc/fsl/qe/ucc_slow.c 	out_be16(&uccs->us_pram->tbase, uccs->tx_base_offset);
tx_base_offset    358 drivers/soc/fsl/qe/ucc_slow.c 	if (uccs->tx_base_offset)
tx_base_offset    359 drivers/soc/fsl/qe/ucc_slow.c 		qe_muram_free(uccs->tx_base_offset);
tx_base_offset    197 include/soc/fsl/qe/ucc_slow.h 	u32 tx_base_offset;	/* first BD in Tx BD table offset (In MURAM) */