ttu_attr          579 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c 		struct _vcs_dpi_display_ttu_regs_st *ttu_attr)
ttu_attr          642 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c 		QoS_LEVEL_LOW_WM, ttu_attr->qos_level_low_wm,
ttu_attr          643 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c 		QoS_LEVEL_HIGH_WM, ttu_attr->qos_level_high_wm);
ttu_attr          649 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c 		REFCYC_PER_REQ_DELIVERY, ttu_attr->refcyc_per_req_delivery_l,
ttu_attr          650 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c 		QoS_LEVEL_FIXED, ttu_attr->qos_level_fixed_l,
ttu_attr          651 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c 		QoS_RAMP_DISABLE, ttu_attr->qos_ramp_disable_l);
ttu_attr          654 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c 		REFCYC_PER_REQ_DELIVERY, ttu_attr->refcyc_per_req_delivery_c,
ttu_attr          655 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c 		QoS_LEVEL_FIXED, ttu_attr->qos_level_fixed_c,
ttu_attr          656 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c 		QoS_RAMP_DISABLE, ttu_attr->qos_ramp_disable_c);
ttu_attr          659 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c 		REFCYC_PER_REQ_DELIVERY, ttu_attr->refcyc_per_req_delivery_cur0,
ttu_attr          660 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c 		QoS_LEVEL_FIXED, ttu_attr->qos_level_fixed_cur0,
ttu_attr          661 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c 		QoS_RAMP_DISABLE, ttu_attr->qos_ramp_disable_cur0);
ttu_attr          667 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c 		struct _vcs_dpi_display_ttu_regs_st *ttu_attr,
ttu_attr          675 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c 	hubp1_program_deadline(hubp, dlg_attr, ttu_attr);
ttu_attr          682 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c 		struct _vcs_dpi_display_ttu_regs_st *ttu_attr)
ttu_attr          709 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c 		ttu_attr->refcyc_per_req_delivery_pre_l);
ttu_attr          712 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c 		ttu_attr->refcyc_per_req_delivery_pre_c);
ttu_attr          714 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c 		REFCYC_PER_REQ_DELIVERY_PRE, ttu_attr->refcyc_per_req_delivery_pre_cur0);
ttu_attr          717 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c 		MIN_TTU_VBLANK, ttu_attr->min_ttu_vblank,
ttu_attr          718 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c 		QoS_LEVEL_FLIP, ttu_attr->qos_level_flip);
ttu_attr          851 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c 	struct _vcs_dpi_display_ttu_regs_st *ttu_attr = &s->ttu_attr;
ttu_attr          952 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c 		QoS_LEVEL_LOW_WM, &ttu_attr->qos_level_low_wm,
ttu_attr          953 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c 		QoS_LEVEL_HIGH_WM, &ttu_attr->qos_level_high_wm);
ttu_attr          956 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c 		MIN_TTU_VBLANK, &ttu_attr->min_ttu_vblank,
ttu_attr          957 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c 		QoS_LEVEL_FLIP, &ttu_attr->qos_level_flip);
ttu_attr          963 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c 		REFCYC_PER_REQ_DELIVERY, &ttu_attr->refcyc_per_req_delivery_l,
ttu_attr          964 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c 		QoS_LEVEL_FIXED, &ttu_attr->qos_level_fixed_l,
ttu_attr          965 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c 		QoS_RAMP_DISABLE, &ttu_attr->qos_ramp_disable_l);
ttu_attr          969 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c 		&ttu_attr->refcyc_per_req_delivery_pre_l);
ttu_attr          972 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c 		REFCYC_PER_REQ_DELIVERY, &ttu_attr->refcyc_per_req_delivery_c,
ttu_attr          973 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c 		QoS_LEVEL_FIXED, &ttu_attr->qos_level_fixed_c,
ttu_attr          974 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c 		QoS_RAMP_DISABLE, &ttu_attr->qos_ramp_disable_c);
ttu_attr          978 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c 		&ttu_attr->refcyc_per_req_delivery_pre_c);
ttu_attr          633 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h 	struct _vcs_dpi_display_ttu_regs_st ttu_attr;
ttu_attr          673 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h 		struct _vcs_dpi_display_ttu_regs_st *ttu_attr);
ttu_attr          226 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 		struct _vcs_dpi_display_ttu_regs_st *ttu_regs = &s->ttu_attr;
ttu_attr          304 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer_debug.c 		struct _vcs_dpi_display_ttu_regs_st *ttu_regs = &s->ttu_attr;
ttu_attr           80 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c 		struct _vcs_dpi_display_ttu_regs_st *ttu_attr)
ttu_attr          143 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c 		QoS_LEVEL_LOW_WM, ttu_attr->qos_level_low_wm,
ttu_attr          144 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c 		QoS_LEVEL_HIGH_WM, ttu_attr->qos_level_high_wm);
ttu_attr          150 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c 		REFCYC_PER_REQ_DELIVERY, ttu_attr->refcyc_per_req_delivery_l,
ttu_attr          151 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c 		QoS_LEVEL_FIXED, ttu_attr->qos_level_fixed_l,
ttu_attr          152 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c 		QoS_RAMP_DISABLE, ttu_attr->qos_ramp_disable_l);
ttu_attr          155 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c 		REFCYC_PER_REQ_DELIVERY, ttu_attr->refcyc_per_req_delivery_c,
ttu_attr          156 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c 		QoS_LEVEL_FIXED, ttu_attr->qos_level_fixed_c,
ttu_attr          157 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c 		QoS_RAMP_DISABLE, ttu_attr->qos_ramp_disable_c);
ttu_attr          160 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c 		REFCYC_PER_REQ_DELIVERY, ttu_attr->refcyc_per_req_delivery_cur0,
ttu_attr          161 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c 		QoS_LEVEL_FIXED, ttu_attr->qos_level_fixed_cur0,
ttu_attr          162 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c 		QoS_RAMP_DISABLE, ttu_attr->qos_ramp_disable_cur0);
ttu_attr          226 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c 		struct _vcs_dpi_display_ttu_regs_st *ttu_attr,
ttu_attr          236 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c 	hubp2_program_deadline(hubp, dlg_attr, ttu_attr);
ttu_attr          243 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c 		struct _vcs_dpi_display_ttu_regs_st *ttu_attr)
ttu_attr          277 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c 		ttu_attr->refcyc_per_req_delivery_pre_l);
ttu_attr          280 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c 		ttu_attr->refcyc_per_req_delivery_pre_c);
ttu_attr          282 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c 		REFCYC_PER_REQ_DELIVERY_PRE, ttu_attr->refcyc_per_req_delivery_pre_cur0);
ttu_attr          284 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c 		REFCYC_PER_REQ_DELIVERY_PRE, ttu_attr->refcyc_per_req_delivery_pre_cur1);
ttu_attr          287 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c 		MIN_TTU_VBLANK, ttu_attr->min_ttu_vblank,
ttu_attr          288 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c 		QoS_LEVEL_FLIP, ttu_attr->qos_level_flip);
ttu_attr         1049 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c 	struct _vcs_dpi_display_ttu_regs_st *ttu_attr = &s->ttu_attr;
ttu_attr         1150 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c 		QoS_LEVEL_LOW_WM, &ttu_attr->qos_level_low_wm,
ttu_attr         1151 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c 		QoS_LEVEL_HIGH_WM, &ttu_attr->qos_level_high_wm);
ttu_attr         1154 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c 		MIN_TTU_VBLANK, &ttu_attr->min_ttu_vblank,
ttu_attr         1155 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c 		QoS_LEVEL_FLIP, &ttu_attr->qos_level_flip);
ttu_attr         1161 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c 		REFCYC_PER_REQ_DELIVERY, &ttu_attr->refcyc_per_req_delivery_l,
ttu_attr         1162 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c 		QoS_LEVEL_FIXED, &ttu_attr->qos_level_fixed_l,
ttu_attr         1163 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c 		QoS_RAMP_DISABLE, &ttu_attr->qos_ramp_disable_l);
ttu_attr         1167 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c 		&ttu_attr->refcyc_per_req_delivery_pre_l);
ttu_attr         1170 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c 		REFCYC_PER_REQ_DELIVERY, &ttu_attr->refcyc_per_req_delivery_c,
ttu_attr         1171 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c 		QoS_LEVEL_FIXED, &ttu_attr->qos_level_fixed_c,
ttu_attr         1172 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c 		QoS_RAMP_DISABLE, &ttu_attr->qos_ramp_disable_c);
ttu_attr         1176 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c 		&ttu_attr->refcyc_per_req_delivery_pre_c);
ttu_attr          243 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.h 		struct _vcs_dpi_display_ttu_regs_st *ttu_attr);
ttu_attr          282 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.h 		struct _vcs_dpi_display_ttu_regs_st *ttu_attr);
ttu_attr          109 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubp.c 		struct _vcs_dpi_display_ttu_regs_st *ttu_attr)
ttu_attr          111 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubp.c 	hubp2_program_deadline(hubp, dlg_attr, ttu_attr);
ttu_attr          151 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubp.c 		struct _vcs_dpi_display_ttu_regs_st *ttu_attr,
ttu_attr          161 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubp.c 	hubp21_program_deadline(hubp, dlg_attr, ttu_attr);
ttu_attr          128 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubp.h 		struct _vcs_dpi_display_ttu_regs_st *ttu_attr);