ttcce             383 drivers/clocksource/timer-cadence-ttc.c 	struct ttc_timer_clockevent *ttcce = container_of(ttc,
ttcce             391 drivers/clocksource/timer-cadence-ttc.c 		clockevents_update_freq(&ttcce->ce, ndata->new_rate / PRESCALE);
ttcce             404 drivers/clocksource/timer-cadence-ttc.c 	struct ttc_timer_clockevent *ttcce;
ttcce             407 drivers/clocksource/timer-cadence-ttc.c 	ttcce = kzalloc(sizeof(*ttcce), GFP_KERNEL);
ttcce             408 drivers/clocksource/timer-cadence-ttc.c 	if (!ttcce)
ttcce             411 drivers/clocksource/timer-cadence-ttc.c 	ttcce->ttc.clk = clk;
ttcce             413 drivers/clocksource/timer-cadence-ttc.c 	err = clk_prepare_enable(ttcce->ttc.clk);
ttcce             415 drivers/clocksource/timer-cadence-ttc.c 		kfree(ttcce);
ttcce             419 drivers/clocksource/timer-cadence-ttc.c 	ttcce->ttc.clk_rate_change_nb.notifier_call =
ttcce             421 drivers/clocksource/timer-cadence-ttc.c 	ttcce->ttc.clk_rate_change_nb.next = NULL;
ttcce             423 drivers/clocksource/timer-cadence-ttc.c 	err = clk_notifier_register(ttcce->ttc.clk,
ttcce             424 drivers/clocksource/timer-cadence-ttc.c 				    &ttcce->ttc.clk_rate_change_nb);
ttcce             430 drivers/clocksource/timer-cadence-ttc.c 	ttcce->ttc.freq = clk_get_rate(ttcce->ttc.clk);
ttcce             432 drivers/clocksource/timer-cadence-ttc.c 	ttcce->ttc.base_addr = base;
ttcce             433 drivers/clocksource/timer-cadence-ttc.c 	ttcce->ce.name = "ttc_clockevent";
ttcce             434 drivers/clocksource/timer-cadence-ttc.c 	ttcce->ce.features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT;
ttcce             435 drivers/clocksource/timer-cadence-ttc.c 	ttcce->ce.set_next_event = ttc_set_next_event;
ttcce             436 drivers/clocksource/timer-cadence-ttc.c 	ttcce->ce.set_state_shutdown = ttc_shutdown;
ttcce             437 drivers/clocksource/timer-cadence-ttc.c 	ttcce->ce.set_state_periodic = ttc_set_periodic;
ttcce             438 drivers/clocksource/timer-cadence-ttc.c 	ttcce->ce.set_state_oneshot = ttc_shutdown;
ttcce             439 drivers/clocksource/timer-cadence-ttc.c 	ttcce->ce.tick_resume = ttc_resume;
ttcce             440 drivers/clocksource/timer-cadence-ttc.c 	ttcce->ce.rating = 200;
ttcce             441 drivers/clocksource/timer-cadence-ttc.c 	ttcce->ce.irq = irq;
ttcce             442 drivers/clocksource/timer-cadence-ttc.c 	ttcce->ce.cpumask = cpu_possible_mask;
ttcce             449 drivers/clocksource/timer-cadence-ttc.c 	writel_relaxed(0x23, ttcce->ttc.base_addr + TTC_CNT_CNTRL_OFFSET);
ttcce             451 drivers/clocksource/timer-cadence-ttc.c 		     ttcce->ttc.base_addr + TTC_CLK_CNTRL_OFFSET);
ttcce             452 drivers/clocksource/timer-cadence-ttc.c 	writel_relaxed(0x1,  ttcce->ttc.base_addr + TTC_IER_OFFSET);
ttcce             455 drivers/clocksource/timer-cadence-ttc.c 			  IRQF_TIMER, ttcce->ce.name, ttcce);
ttcce             457 drivers/clocksource/timer-cadence-ttc.c 		kfree(ttcce);
ttcce             461 drivers/clocksource/timer-cadence-ttc.c 	clockevents_config_and_register(&ttcce->ce,
ttcce             462 drivers/clocksource/timer-cadence-ttc.c 			ttcce->ttc.freq / PRESCALE, 1, 0xfffe);