ttbr 160 arch/arm/include/asm/proc-fns.h u64 ttbr; \ ttbr 162 arch/arm/include/asm/proc-fns.h : "=r" (ttbr)); \ ttbr 163 arch/arm/include/asm/proc-fns.h ttbr; \ ttbr 537 arch/arm64/include/asm/assembler.h .macro offset_ttbr1, ttbr, tmp ttbr 552 arch/arm64/include/asm/assembler.h .macro restore_ttbr1, ttbr ttbr 565 arch/arm64/include/asm/assembler.h .macro phys_to_ttbr, ttbr, phys ttbr 43 arch/arm64/include/asm/mmu_context.h unsigned long ttbr = phys_to_ttbr(__pa_symbol(empty_zero_page)); ttbr 45 arch/arm64/include/asm/mmu_context.h write_sysreg(ttbr, ttbr0_el1); ttbr 184 arch/arm64/include/asm/mmu_context.h u64 ttbr; ttbr 190 arch/arm64/include/asm/mmu_context.h ttbr = __pa_symbol(empty_zero_page); ttbr 192 arch/arm64/include/asm/mmu_context.h ttbr = virt_to_phys(mm->pgd) | ASID(mm) << 48; ttbr 194 arch/arm64/include/asm/mmu_context.h WRITE_ONCE(task_thread_info(tsk)->ttbr0, ttbr); ttbr 110 arch/arm64/include/asm/uaccess.h unsigned long flags, ttbr; ttbr 113 arch/arm64/include/asm/uaccess.h ttbr = read_sysreg(ttbr1_el1); ttbr 114 arch/arm64/include/asm/uaccess.h ttbr &= ~TTBR_ASID_MASK; ttbr 116 arch/arm64/include/asm/uaccess.h write_sysreg(ttbr - RESERVED_TTBR0_SIZE, ttbr0_el1); ttbr 119 arch/arm64/include/asm/uaccess.h write_sysreg(ttbr, ttbr1_el1); ttbr 556 drivers/iommu/arm-smmu-v3.c u64 ttbr; ttbr 1487 drivers/iommu/arm-smmu-v3.c val = cfg->cd.ttbr & CTXDESC_CD_1_TTB0_MASK; ttbr 2175 drivers/iommu/arm-smmu-v3.c cfg->cd.ttbr = pgtbl_cfg->arm_lpae_s1_cfg.ttbr[0]; ttbr 94 drivers/iommu/arm-smmu.c u64 ttbr[2]; ttbr 521 drivers/iommu/arm-smmu.c cb->ttbr[0] = pgtbl_cfg->arm_v7s_cfg.ttbr[0]; ttbr 522 drivers/iommu/arm-smmu.c cb->ttbr[1] = pgtbl_cfg->arm_v7s_cfg.ttbr[1]; ttbr 524 drivers/iommu/arm-smmu.c cb->ttbr[0] = pgtbl_cfg->arm_lpae_s1_cfg.ttbr[0]; ttbr 525 drivers/iommu/arm-smmu.c cb->ttbr[0] |= FIELD_PREP(TTBRn_ASID, cfg->asid); ttbr 526 drivers/iommu/arm-smmu.c cb->ttbr[1] = pgtbl_cfg->arm_lpae_s1_cfg.ttbr[1]; ttbr 527 drivers/iommu/arm-smmu.c cb->ttbr[1] |= FIELD_PREP(TTBRn_ASID, cfg->asid); ttbr 530 drivers/iommu/arm-smmu.c cb->ttbr[0] = pgtbl_cfg->arm_lpae_s2_cfg.vttbr; ttbr 603 drivers/iommu/arm-smmu.c arm_smmu_cb_write(smmu, idx, ARM_SMMU_CB_TTBR0, cb->ttbr[0]); ttbr 604 drivers/iommu/arm-smmu.c arm_smmu_cb_write(smmu, idx, ARM_SMMU_CB_TTBR1, cb->ttbr[1]); ttbr 606 drivers/iommu/arm-smmu.c arm_smmu_cb_writeq(smmu, idx, ARM_SMMU_CB_TTBR0, cb->ttbr[0]); ttbr 609 drivers/iommu/arm-smmu.c cb->ttbr[1]); ttbr 826 drivers/iommu/io-pgtable-arm-v7s.c cfg->arm_v7s_cfg.ttbr[0] = virt_to_phys(data->pgd) | ttbr 833 drivers/iommu/io-pgtable-arm-v7s.c cfg->arm_v7s_cfg.ttbr[1] = 0; ttbr 879 drivers/iommu/io-pgtable-arm.c cfg->arm_lpae_s1_cfg.ttbr[0] = virt_to_phys(data->pgd); ttbr 880 drivers/iommu/io-pgtable-arm.c cfg->arm_lpae_s1_cfg.ttbr[1] = 0; ttbr 415 drivers/iommu/ipmmu-vmsa.c u64 ttbr; ttbr 419 drivers/iommu/ipmmu-vmsa.c ttbr = domain->cfg.arm_lpae_s1_cfg.ttbr[0]; ttbr 420 drivers/iommu/ipmmu-vmsa.c ipmmu_ctx_write_root(domain, IMTTLBR0, ttbr); ttbr 421 drivers/iommu/ipmmu-vmsa.c ipmmu_ctx_write_root(domain, IMTTUBR0, ttbr >> 32); ttbr 282 drivers/iommu/msm_iommu.c SET_TTBR0(base, ctx, priv->cfg.arm_v7s_cfg.ttbr[0]); ttbr 283 drivers/iommu/msm_iommu.c SET_TTBR1(base, ctx, priv->cfg.arm_v7s_cfg.ttbr[1]); ttbr 410 drivers/iommu/mtk_iommu.c writel(dom->cfg.arm_v7s_cfg.ttbr[0] & MMU_PT_ADDR_MASK, ttbr 821 drivers/iommu/mtk_iommu.c writel(m4u_dom->cfg.arm_v7s_cfg.ttbr[0] & MMU_PT_ADDR_MASK, ttbr 272 drivers/iommu/qcom_iommu.c pgtbl_cfg.arm_lpae_s1_cfg.ttbr[0] | ttbr 275 drivers/iommu/qcom_iommu.c pgtbl_cfg.arm_lpae_s1_cfg.ttbr[1] | ttbr 103 include/linux/io-pgtable.h u64 ttbr[2]; ttbr 114 include/linux/io-pgtable.h u32 ttbr[2];