TX0_A             924 drivers/pinctrl/sh-pfc/pfc-r8a77470.c 	PINMUX_IPSR_MSEL(IP12_3_0, TX0_A, SEL_SCIF0_0),
TX0_A             727 drivers/pinctrl/sh-pfc/pfc-r8a7778.c 	PINMUX_IPSR_GPSR(IP3_9_8,	TX0_A),
TX0_A            1463 drivers/pinctrl/sh-pfc/pfc-r8a7778.c SCIF_PFC_DAT(scif0_data_a,	TX0_A,			RX0_A);
TX0_A             189 drivers/pinctrl/sh-pfc/pfc-r8a77990.c #define GPSR5_2		F_(TX0_A,		IP11_15_12)
TX0_A             309 drivers/pinctrl/sh-pfc/pfc-r8a77990.c #define IP11_15_12	FM(TX0_A)		FM(HTX1_A)		FM(SSI_WS2_A)		FM(RIF1_D0)		F_(0, 0)		F_(0, 0)	F_(0, 0)	FM(TS_SDAT1)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
TX0_A            1095 drivers/pinctrl/sh-pfc/pfc-r8a77990.c 	PINMUX_IPSR_MSEL(IP11_15_12,		TX0_A,		SEL_SCIF0_0),
TX0_A             136 drivers/pinctrl/sh-pfc/pfc-r8a77995.c #define GPSR4_21	F_(TX0_A,		IP11_27_24)
TX0_A             297 drivers/pinctrl/sh-pfc/pfc-r8a77995.c #define IP11_27_24	FM(TX0_A)		FM(MSIOF0_SS2)		FM(FSO_TOE_N_B)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
TX0_A             880 drivers/pinctrl/sh-pfc/pfc-r8a77995.c 	PINMUX_IPSR_MSEL(IP11_27_24,	TX0_A, SEL_SCIF0_0),
TX0_A            1314 drivers/pinctrl/sh-pfc/pfc-sh7734.c 	PINMUX_IPSR_MSEL(IP11_12, TX0_A, SEL_SCIF0_0),
TX0_A            1624 drivers/pinctrl/sh-pfc/pfc-sh7734.c 	GPIO_FN(TX0_A), GPIO_FN(HSPI_TX_A),
TX0_A            1090 drivers/staging/rtl8723bs/hal/HalPhyRf_8723B.c 	u32 Oldval_0, X, TX0_A, reg;
TX0_A            1108 drivers/staging/rtl8723bs/hal/HalPhyRf_8723B.c 		TX0_A = (X * Oldval_0) >> 8;
TX0_A            1109 drivers/staging/rtl8723bs/hal/HalPhyRf_8723B.c 		ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD,  ("X = 0x%x, TX0_A = 0x%x, Oldval_0 0x%x\n", X, TX0_A, Oldval_0));
TX0_A            1110 drivers/staging/rtl8723bs/hal/HalPhyRf_8723B.c 		PHY_SetBBReg(pDM_Odm->Adapter, rOFDM0_XATxIQImbalance, 0x3FF, TX0_A);