train_set 208 drivers/gpu/drm/amd/amdgpu/atombios_dp.c u8 train_set[4]) train_set 240 drivers/gpu/drm/amd/amdgpu/atombios_dp.c train_set[lane] = v | p; train_set 486 drivers/gpu/drm/amd/amdgpu/atombios_dp.c u8 train_set[4]; train_set 498 drivers/gpu/drm/amd/amdgpu/atombios_dp.c 0, dp_info->train_set[0]); /* sets all lanes at once */ train_set 502 drivers/gpu/drm/amd/amdgpu/atombios_dp.c dp_info->train_set, dp_info->dp_lane_count); train_set 596 drivers/gpu/drm/amd/amdgpu/atombios_dp.c memset(dp_info->train_set, 0, 4); train_set 620 drivers/gpu/drm/amd/amdgpu/atombios_dp.c if ((dp_info->train_set[i] & DP_TRAIN_MAX_SWING_REACHED) == 0) train_set 628 drivers/gpu/drm/amd/amdgpu/atombios_dp.c if ((dp_info->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) == voltage) { train_set 637 drivers/gpu/drm/amd/amdgpu/atombios_dp.c voltage = dp_info->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK; train_set 641 drivers/gpu/drm/amd/amdgpu/atombios_dp.c dp_info->train_set); train_set 650 drivers/gpu/drm/amd/amdgpu/atombios_dp.c dp_info->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK, train_set 651 drivers/gpu/drm/amd/amdgpu/atombios_dp.c (dp_info->train_set[0] & DP_TRAIN_PRE_EMPHASIS_MASK) >> train_set 692 drivers/gpu/drm/amd/amdgpu/atombios_dp.c dp_info->train_set); train_set 703 drivers/gpu/drm/amd/amdgpu/atombios_dp.c dp_info->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK, train_set 704 drivers/gpu/drm/amd/amdgpu/atombios_dp.c (dp_info->train_set[0] & DP_TRAIN_PRE_EMPHASIS_MASK) train_set 270 drivers/gpu/drm/gma500/cdv_intel_dp.c uint8_t train_set[4]; train_set 1330 drivers/gpu/drm/gma500/cdv_intel_dp.c intel_dp->train_set[lane] = v | p; train_set 1421 drivers/gpu/drm/gma500/cdv_intel_dp.c intel_dp->train_set, train_set 1426 drivers/gpu/drm/gma500/cdv_intel_dp.c intel_dp->train_set[0], intel_dp->lane_count); train_set 1526 drivers/gpu/drm/gma500/cdv_intel_dp.c memset(intel_dp->train_set, 0, 4); train_set 1538 drivers/gpu/drm/gma500/cdv_intel_dp.c intel_dp->train_set[0], train_set 1545 drivers/gpu/drm/gma500/cdv_intel_dp.c cdv_intel_dp_set_vswing_premph(encoder, intel_dp->train_set[0]); train_set 1566 drivers/gpu/drm/gma500/cdv_intel_dp.c if ((intel_dp->train_set[i] & DP_TRAIN_MAX_SWING_REACHED) == 0) train_set 1572 drivers/gpu/drm/gma500/cdv_intel_dp.c if ((intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) == voltage) { train_set 1578 drivers/gpu/drm/gma500/cdv_intel_dp.c voltage = intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK; train_set 1586 drivers/gpu/drm/gma500/cdv_intel_dp.c DRM_DEBUG_KMS("failure in DP patter 1 training, train set %x\n", intel_dp->train_set[0]); train_set 1613 drivers/gpu/drm/gma500/cdv_intel_dp.c intel_dp->train_set[0], train_set 1630 drivers/gpu/drm/gma500/cdv_intel_dp.c cdv_intel_dp_set_vswing_premph(encoder, intel_dp->train_set[0]); train_set 2735 drivers/gpu/drm/i915/display/intel_ddi.c u8 train_set = intel_dp->train_set[0]; train_set 2736 drivers/gpu/drm/i915/display/intel_ddi.c int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK | train_set 1180 drivers/gpu/drm/i915/display/intel_display_types.h u8 train_set[4]; train_set 3713 drivers/gpu/drm/i915/display/intel_dp.c u8 train_set = intel_dp->train_set[0]; train_set 3715 drivers/gpu/drm/i915/display/intel_dp.c switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) { train_set 3718 drivers/gpu/drm/i915/display/intel_dp.c switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { train_set 3741 drivers/gpu/drm/i915/display/intel_dp.c switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { train_set 3760 drivers/gpu/drm/i915/display/intel_dp.c switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { train_set 3775 drivers/gpu/drm/i915/display/intel_dp.c switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { train_set 3799 drivers/gpu/drm/i915/display/intel_dp.c u8 train_set = intel_dp->train_set[0]; train_set 3801 drivers/gpu/drm/i915/display/intel_dp.c switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) { train_set 3803 drivers/gpu/drm/i915/display/intel_dp.c switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { train_set 3826 drivers/gpu/drm/i915/display/intel_dp.c switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { train_set 3844 drivers/gpu/drm/i915/display/intel_dp.c switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { train_set 3858 drivers/gpu/drm/i915/display/intel_dp.c switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { train_set 3878 drivers/gpu/drm/i915/display/intel_dp.c g4x_signal_levels(u8 train_set) train_set 3882 drivers/gpu/drm/i915/display/intel_dp.c switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { train_set 3897 drivers/gpu/drm/i915/display/intel_dp.c switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) { train_set 3917 drivers/gpu/drm/i915/display/intel_dp.c snb_cpu_edp_signal_levels(u8 train_set) train_set 3919 drivers/gpu/drm/i915/display/intel_dp.c int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK | train_set 3945 drivers/gpu/drm/i915/display/intel_dp.c ivb_cpu_edp_signal_levels(u8 train_set) train_set 3947 drivers/gpu/drm/i915/display/intel_dp.c int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK | train_set 3981 drivers/gpu/drm/i915/display/intel_dp.c u8 train_set = intel_dp->train_set[0]; train_set 3993 drivers/gpu/drm/i915/display/intel_dp.c signal_levels = ivb_cpu_edp_signal_levels(train_set); train_set 3996 drivers/gpu/drm/i915/display/intel_dp.c signal_levels = snb_cpu_edp_signal_levels(train_set); train_set 3999 drivers/gpu/drm/i915/display/intel_dp.c signal_levels = g4x_signal_levels(train_set); train_set 4007 drivers/gpu/drm/i915/display/intel_dp.c train_set & DP_TRAIN_VOLTAGE_SWING_MASK); train_set 4009 drivers/gpu/drm/i915/display/intel_dp.c (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) >> train_set 66 drivers/gpu/drm/i915/display/intel_dp_link_training.c intel_dp->train_set[lane] = v | p; train_set 73 drivers/gpu/drm/i915/display/intel_dp_link_training.c u8 buf[sizeof(intel_dp->train_set) + 1]; train_set 85 drivers/gpu/drm/i915/display/intel_dp_link_training.c memcpy(buf + 1, intel_dp->train_set, intel_dp->lane_count); train_set 99 drivers/gpu/drm/i915/display/intel_dp_link_training.c memset(intel_dp->train_set, 0, sizeof(intel_dp->train_set)); train_set 112 drivers/gpu/drm/i915/display/intel_dp_link_training.c intel_dp->train_set, intel_dp->lane_count); train_set 122 drivers/gpu/drm/i915/display/intel_dp_link_training.c if ((intel_dp->train_set[lane] & train_set 215 drivers/gpu/drm/i915/display/intel_dp_link_training.c voltage = intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK; train_set 224 drivers/gpu/drm/i915/display/intel_dp_link_training.c if ((intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) == train_set 258 drivers/gpu/drm/radeon/atombios_dp.c u8 train_set[4]) train_set 290 drivers/gpu/drm/radeon/atombios_dp.c train_set[lane] = v | p; train_set 548 drivers/gpu/drm/radeon/atombios_dp.c u8 train_set[4]; train_set 560 drivers/gpu/drm/radeon/atombios_dp.c 0, dp_info->train_set[0]); /* sets all lanes at once */ train_set 564 drivers/gpu/drm/radeon/atombios_dp.c dp_info->train_set, dp_info->dp_lane_count); train_set 675 drivers/gpu/drm/radeon/atombios_dp.c memset(dp_info->train_set, 0, 4); train_set 699 drivers/gpu/drm/radeon/atombios_dp.c if ((dp_info->train_set[i] & DP_TRAIN_MAX_SWING_REACHED) == 0) train_set 707 drivers/gpu/drm/radeon/atombios_dp.c if ((dp_info->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) == voltage) { train_set 716 drivers/gpu/drm/radeon/atombios_dp.c voltage = dp_info->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK; train_set 719 drivers/gpu/drm/radeon/atombios_dp.c dp_get_adjust_train(dp_info->link_status, dp_info->dp_lane_count, dp_info->train_set); train_set 728 drivers/gpu/drm/radeon/atombios_dp.c dp_info->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK, train_set 729 drivers/gpu/drm/radeon/atombios_dp.c (dp_info->train_set[0] & DP_TRAIN_PRE_EMPHASIS_MASK) >> train_set 768 drivers/gpu/drm/radeon/atombios_dp.c dp_get_adjust_train(dp_info->link_status, dp_info->dp_lane_count, dp_info->train_set); train_set 779 drivers/gpu/drm/radeon/atombios_dp.c dp_info->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK, train_set 780 drivers/gpu/drm/radeon/atombios_dp.c (dp_info->train_set[0] & DP_TRAIN_PRE_EMPHASIS_MASK)