CM_DGAM_LUT_WRITE_EN_MASK  110 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h 	SRI(CM_DGAM_LUT_WRITE_EN_MASK, CM, id), \
CM_DGAM_LUT_WRITE_EN_MASK  313 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h 	TF_SF(CM0_CM_DGAM_LUT_WRITE_EN_MASK, CM_DGAM_LUT_WRITE_EN_MASK, mask_sh), \
CM_DGAM_LUT_WRITE_EN_MASK 1053 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h 	type CM_DGAM_LUT_WRITE_EN_MASK; \
CM_DGAM_LUT_WRITE_EN_MASK 1319 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h 	uint32_t CM_DGAM_LUT_WRITE_EN_MASK; \
CM_DGAM_LUT_WRITE_EN_MASK  679 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c 	REG_UPDATE(CM_DGAM_LUT_WRITE_EN_MASK,
CM_DGAM_LUT_WRITE_EN_MASK  680 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c 				   CM_DGAM_LUT_WRITE_EN_MASK, 7);
CM_DGAM_LUT_WRITE_EN_MASK  681 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c 	REG_UPDATE(CM_DGAM_LUT_WRITE_EN_MASK, CM_DGAM_LUT_WRITE_SEL,
CM_DGAM_LUT_WRITE_EN_MASK   72 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp_cm.c 	REG_GET(CM_DGAM_LUT_WRITE_EN_MASK, CM_DGAM_CONFIG_STATUS,
CM_DGAM_LUT_WRITE_EN_MASK   94 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp_cm.c 	REG_UPDATE(CM_DGAM_LUT_WRITE_EN_MASK,
CM_DGAM_LUT_WRITE_EN_MASK   95 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp_cm.c 				CM_DGAM_LUT_WRITE_EN_MASK, 7);
CM_DGAM_LUT_WRITE_EN_MASK   96 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp_cm.c 	REG_UPDATE(CM_DGAM_LUT_WRITE_EN_MASK, CM_DGAM_LUT_WRITE_SEL,