CM_DGAM_LUT_MODE  106 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c 			CM_DGAM_LUT_MODE, &s->dgam_lut_mode);
CM_DGAM_LUT_MODE  317 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h 	TF_SF(CM0_CM_DGAM_CONTROL, CM_DGAM_LUT_MODE, mask_sh), \
CM_DGAM_LUT_MODE 1057 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h 	type CM_DGAM_LUT_MODE; \
CM_DGAM_LUT_MODE  621 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c 		REG_UPDATE(CM_DGAM_CONTROL, CM_DGAM_LUT_MODE, 0);
CM_DGAM_LUT_MODE  624 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c 		REG_UPDATE(CM_DGAM_CONTROL, CM_DGAM_LUT_MODE, 1);
CM_DGAM_LUT_MODE  627 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c 		REG_UPDATE(CM_DGAM_CONTROL, CM_DGAM_LUT_MODE, 2);
CM_DGAM_LUT_MODE  642 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c 		REG_UPDATE(CM_DGAM_CONTROL, CM_DGAM_LUT_MODE, 3);
CM_DGAM_LUT_MODE  644 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c 		REG_UPDATE(CM_DGAM_CONTROL, CM_DGAM_LUT_MODE, 4);
CM_DGAM_LUT_MODE  740 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c 	REG_SET(CM_DGAM_CONTROL, 0, CM_DGAM_LUT_MODE, 0);
CM_DGAM_LUT_MODE   59 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.c 			CM_DGAM_LUT_MODE, &s->dgam_lut_mode);
CM_DGAM_LUT_MODE  144 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp_cm.c 		REG_UPDATE(CM_DGAM_CONTROL, CM_DGAM_LUT_MODE, 0);
CM_DGAM_LUT_MODE  147 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp_cm.c 		REG_UPDATE(CM_DGAM_CONTROL, CM_DGAM_LUT_MODE, 1);
CM_DGAM_LUT_MODE  150 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp_cm.c 		REG_UPDATE(CM_DGAM_CONTROL, CM_DGAM_LUT_MODE, 2);