CM_DGAM_CONTROL   105 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c 	REG_GET(CM_DGAM_CONTROL,
CM_DGAM_CONTROL   114 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h 	SRI(CM_DGAM_CONTROL, CM, id), \
CM_DGAM_CONTROL  1323 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h 	uint32_t CM_DGAM_CONTROL; \
CM_DGAM_CONTROL   621 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c 		REG_UPDATE(CM_DGAM_CONTROL, CM_DGAM_LUT_MODE, 0);
CM_DGAM_CONTROL   624 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c 		REG_UPDATE(CM_DGAM_CONTROL, CM_DGAM_LUT_MODE, 1);
CM_DGAM_CONTROL   627 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c 		REG_UPDATE(CM_DGAM_CONTROL, CM_DGAM_LUT_MODE, 2);
CM_DGAM_CONTROL   642 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c 		REG_UPDATE(CM_DGAM_CONTROL, CM_DGAM_LUT_MODE, 3);
CM_DGAM_CONTROL   644 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c 		REG_UPDATE(CM_DGAM_CONTROL, CM_DGAM_LUT_MODE, 4);
CM_DGAM_CONTROL   740 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c 	REG_SET(CM_DGAM_CONTROL, 0, CM_DGAM_LUT_MODE, 0);
CM_DGAM_CONTROL    58 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.c 	REG_GET(CM_DGAM_CONTROL,
CM_DGAM_CONTROL   144 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp_cm.c 		REG_UPDATE(CM_DGAM_CONTROL, CM_DGAM_LUT_MODE, 0);
CM_DGAM_CONTROL   147 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp_cm.c 		REG_UPDATE(CM_DGAM_CONTROL, CM_DGAM_LUT_MODE, 1);
CM_DGAM_CONTROL   150 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp_cm.c 		REG_UPDATE(CM_DGAM_CONTROL, CM_DGAM_LUT_MODE, 2);