CM_CONTROL        113 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h 	SRI(CM_CONTROL, CM, id), \
CM_CONTROL       1322 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h 	uint32_t CM_CONTROL; \
CM_CONTROL        608 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c 	REG_UPDATE(CM_CONTROL, CM_BYPASS_EN, 0);
CM_CONTROL        733 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c 		REG_SET(CM_CONTROL, 0, CM_BYPASS_EN, 1);
CM_CONTROL        736 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c 		REG_SET(CM_CONTROL, 0, CM_BYPASS, 1);
CM_CONTROL         60 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp_cm.c 	REG_UPDATE(CM_CONTROL, CM_BYPASS, cm_bypass_mode);