tpu 5417 drivers/pinctrl/sh-pfc/pfc-r8a7791.c SH_PFC_FUNCTION(tpu), tpu 4613 drivers/pinctrl/sh-pfc/pfc-r8a7794.c SH_PFC_FUNCTION(tpu), tpu 4741 drivers/pinctrl/sh-pfc/pfc-r8a7795-es1.c SH_PFC_FUNCTION(tpu), tpu 5084 drivers/pinctrl/sh-pfc/pfc-r8a7795.c SH_PFC_FUNCTION(tpu), tpu 5047 drivers/pinctrl/sh-pfc/pfc-r8a7796.c SH_PFC_FUNCTION(tpu), tpu 5294 drivers/pinctrl/sh-pfc/pfc-r8a77965.c SH_PFC_FUNCTION(tpu), tpu 2469 drivers/pinctrl/sh-pfc/pfc-r8a77980.c SH_PFC_FUNCTION(tpu), tpu 72 drivers/pwm/pwm-renesas-tpu.c struct tpu_device *tpu; tpu 94 drivers/pwm/pwm-renesas-tpu.c void __iomem *base = pwm->tpu->base + TPU_CHANNEL_OFFSET tpu 105 drivers/pwm/pwm-renesas-tpu.c dev_dbg(&pwm->tpu->pdev->dev, "%u: configuring pin as %s\n", tpu 132 drivers/pwm/pwm-renesas-tpu.c spin_lock_irqsave(&pwm->tpu->lock, flags); tpu 133 drivers/pwm/pwm-renesas-tpu.c value = ioread16(pwm->tpu->base + TPU_TSTR); tpu 140 drivers/pwm/pwm-renesas-tpu.c iowrite16(value, pwm->tpu->base + TPU_TSTR); tpu 141 drivers/pwm/pwm-renesas-tpu.c spin_unlock_irqrestore(&pwm->tpu->lock, flags); tpu 150 drivers/pwm/pwm-renesas-tpu.c pm_runtime_get_sync(&pwm->tpu->pdev->dev); tpu 151 drivers/pwm/pwm-renesas-tpu.c ret = clk_prepare_enable(pwm->tpu->clk); tpu 153 drivers/pwm/pwm-renesas-tpu.c dev_err(&pwm->tpu->pdev->dev, "cannot enable clock\n"); tpu 182 drivers/pwm/pwm-renesas-tpu.c dev_dbg(&pwm->tpu->pdev->dev, "%u: TGRA 0x%04x TGRB 0x%04x\n", tpu 200 drivers/pwm/pwm-renesas-tpu.c clk_disable_unprepare(pwm->tpu->clk); tpu 201 drivers/pwm/pwm-renesas-tpu.c pm_runtime_put(&pwm->tpu->pdev->dev); tpu 212 drivers/pwm/pwm-renesas-tpu.c struct tpu_device *tpu = to_tpu_device(chip); tpu 222 drivers/pwm/pwm-renesas-tpu.c pwm->tpu = tpu; tpu 249 drivers/pwm/pwm-renesas-tpu.c struct tpu_device *tpu = to_tpu_device(chip); tpu 261 drivers/pwm/pwm-renesas-tpu.c clk_rate = clk_get_rate(tpu->clk); tpu 271 drivers/pwm/pwm-renesas-tpu.c dev_err(&tpu->pdev->dev, "clock rate mismatch\n"); tpu 284 drivers/pwm/pwm-renesas-tpu.c dev_dbg(&tpu->pdev->dev, tpu 306 drivers/pwm/pwm-renesas-tpu.c dev_dbg(&tpu->pdev->dev, "%u: TGRA 0x%04x\n", pwm->channel, tpu 385 drivers/pwm/pwm-renesas-tpu.c struct tpu_device *tpu; tpu 389 drivers/pwm/pwm-renesas-tpu.c tpu = devm_kzalloc(&pdev->dev, sizeof(*tpu), GFP_KERNEL); tpu 390 drivers/pwm/pwm-renesas-tpu.c if (tpu == NULL) tpu 393 drivers/pwm/pwm-renesas-tpu.c spin_lock_init(&tpu->lock); tpu 394 drivers/pwm/pwm-renesas-tpu.c tpu->pdev = pdev; tpu 398 drivers/pwm/pwm-renesas-tpu.c tpu->base = devm_ioremap_resource(&pdev->dev, res); tpu 399 drivers/pwm/pwm-renesas-tpu.c if (IS_ERR(tpu->base)) tpu 400 drivers/pwm/pwm-renesas-tpu.c return PTR_ERR(tpu->base); tpu 402 drivers/pwm/pwm-renesas-tpu.c tpu->clk = devm_clk_get(&pdev->dev, NULL); tpu 403 drivers/pwm/pwm-renesas-tpu.c if (IS_ERR(tpu->clk)) { tpu 405 drivers/pwm/pwm-renesas-tpu.c return PTR_ERR(tpu->clk); tpu 409 drivers/pwm/pwm-renesas-tpu.c platform_set_drvdata(pdev, tpu); tpu 411 drivers/pwm/pwm-renesas-tpu.c tpu->chip.dev = &pdev->dev; tpu 412 drivers/pwm/pwm-renesas-tpu.c tpu->chip.ops = &tpu_pwm_ops; tpu 413 drivers/pwm/pwm-renesas-tpu.c tpu->chip.of_xlate = of_pwm_xlate_with_flags; tpu 414 drivers/pwm/pwm-renesas-tpu.c tpu->chip.of_pwm_n_cells = 3; tpu 415 drivers/pwm/pwm-renesas-tpu.c tpu->chip.base = -1; tpu 416 drivers/pwm/pwm-renesas-tpu.c tpu->chip.npwm = TPU_CHANNEL_MAX; tpu 420 drivers/pwm/pwm-renesas-tpu.c ret = pwmchip_add(&tpu->chip); tpu 427 drivers/pwm/pwm-renesas-tpu.c dev_info(&pdev->dev, "TPU PWM %d registered\n", tpu->pdev->id); tpu 434 drivers/pwm/pwm-renesas-tpu.c struct tpu_device *tpu = platform_get_drvdata(pdev); tpu 437 drivers/pwm/pwm-renesas-tpu.c ret = pwmchip_remove(&tpu->chip);