tp_intr            73 drivers/net/ethernet/chelsio/cxgb/tp.c 	u32 tp_intr = readl(tp->adapter->regs + A_PL_ENABLE);
tp_intr            80 drivers/net/ethernet/chelsio/cxgb/tp.c 		writel(tp_intr | FPGA_PCIX_INTERRUPT_TP,
tp_intr            87 drivers/net/ethernet/chelsio/cxgb/tp.c 		writel(tp_intr | F_PL_INTR_TP,
tp_intr            94 drivers/net/ethernet/chelsio/cxgb/tp.c 	u32 tp_intr = readl(tp->adapter->regs + A_PL_ENABLE);
tp_intr           100 drivers/net/ethernet/chelsio/cxgb/tp.c 		writel(tp_intr & ~FPGA_PCIX_INTERRUPT_TP,
tp_intr           106 drivers/net/ethernet/chelsio/cxgb/tp.c 		writel(tp_intr & ~F_PL_INTR_TP,