total_fl          142 drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c 	u32 total_fl;
total_fl          167 drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c 			total_fl = (fixed_buff_size / 2) /
total_fl          171 drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c 			total_fl = (fixed_buff_size / 2) * 2 /
total_fl          176 drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c 			total_fl = (fixed_buff_size / 2) * 2 /
total_fl          179 drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c 			total_fl = (fixed_buff_size) * 2 /
total_fl          187 drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c 			src_width, total_fl);
total_fl          189 drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c 	return total_fl;
total_fl          199 drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c 		u32 total_fl)
total_fl          207 drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c 		if (total_fl <= tbl->entries[i].fl)
total_fl          228 drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c 	u32 total_fl = 0, lut_usage;
total_fl          236 drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c 		total_fl = _dpu_plane_calc_fill_level(plane, fmt,
total_fl          246 drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c 			&pdpu->catalog->perf.qos_lut_tbl[lut_usage], total_fl);
total_fl          252 drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c 			pdpu->is_rt_pipe, total_fl, qos_lut, lut_usage);
total_fl          258 drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c 			pdpu->is_rt_pipe, total_fl, qos_lut);