top_sel           129 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c 	unsigned int top_sel;
top_sel           133 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c 	REG_GET(MPCC_TOP_SEL[mpcc_id], MPCC_TOP_SEL, &top_sel);
top_sel           136 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c 	if (top_sel == 0xf && opp_id == 0xf && idle)
top_sel           145 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c 	unsigned int top_sel, mpc_busy, mpc_idle;
top_sel           148 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c 			MPCC_TOP_SEL, &top_sel);
top_sel           150 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c 	if (top_sel == 0xf) {
top_sel           391 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c 	unsigned int top_sel;
top_sel           403 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c 			REG_GET(MPCC_TOP_SEL[mpcc_id], MPCC_TOP_SEL, &top_sel);
top_sel           409 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c 			if ((opp_id == tree->opp_id) && (top_sel != 0xf)) {
top_sel           411 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c 				mpcc->dpp_id = top_sel;
top_sel           419 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c 					REG_GET(MPCC_TOP_SEL[bot_mpcc_id], MPCC_TOP_SEL, &top_sel);
top_sel           420 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c 					if ((opp_id == tree->opp_id) && (top_sel != 0xf)) {
top_sel           448 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.c 	unsigned int top_sel, mpc_busy, mpc_idle, mpc_disabled;
top_sel           451 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.c 			MPCC_TOP_SEL, &top_sel);
top_sel           458 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.c 	if (top_sel == 0xf) {