top_pipe_to_program 2002 drivers/gpu/drm/amd/display/dc/core/dc.c 	struct pipe_ctx *top_pipe_to_program = NULL;
top_pipe_to_program 2070 drivers/gpu/drm/amd/display/dc/core/dc.c 			top_pipe_to_program = pipe_ctx;
top_pipe_to_program 2103 drivers/gpu/drm/amd/display/dc/core/dc.c 		dc->hwss.pipe_control_lock(dc, top_pipe_to_program, true);
top_pipe_to_program 2151 drivers/gpu/drm/amd/display/dc/core/dc.c 		dc->hwss.pipe_control_lock(dc, top_pipe_to_program, false);
top_pipe_to_program 2561 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 	struct pipe_ctx *top_pipe_to_program =
top_pipe_to_program 2565 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 	if (!top_pipe_to_program)
top_pipe_to_program 2568 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 	tg = top_pipe_to_program->stream_res.tg;
top_pipe_to_program 2570 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 	interdependent_update = top_pipe_to_program->plane_state &&
top_pipe_to_program 2571 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 		top_pipe_to_program->plane_state->update_flags.bits.full_update;
top_pipe_to_program 2576 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 		ASSERT(dc->hwss.did_underflow_occur(dc, top_pipe_to_program));
top_pipe_to_program 2581 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 		dcn10_pipe_control_lock(dc, top_pipe_to_program, true);
top_pipe_to_program 2587 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 		ASSERT(dc->hwss.did_underflow_occur(dc, top_pipe_to_program));
top_pipe_to_program 2591 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 		dc->hwss.blank_pixel_data(dc, top_pipe_to_program, true);
top_pipe_to_program 2626 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 		program_all_pipe_in_tree(dc, top_pipe_to_program, context);
top_pipe_to_program 2650 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 		dcn10_pipe_control_lock(dc, top_pipe_to_program, false);
top_pipe_to_program 1156 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c 	struct pipe_ctx *top_pipe_to_program =
top_pipe_to_program 1162 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c 	if (!top_pipe_to_program)
top_pipe_to_program 1177 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c 	tg = top_pipe_to_program->stream_res.tg;
top_pipe_to_program 1179 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c 	interdependent_update = top_pipe_to_program->plane_state &&
top_pipe_to_program 1180 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c 		top_pipe_to_program->plane_state->update_flags.bits.full_update;
top_pipe_to_program 1185 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c 		dcn20_pipe_control_lock(dc, top_pipe_to_program, true);
top_pipe_to_program 1189 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c 		dc->hwss.blank_pixel_data(dc, top_pipe_to_program, true);
top_pipe_to_program 1224 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c 		dcn20_program_all_pipe_in_tree(dc, top_pipe_to_program, context);
top_pipe_to_program 1248 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c 		dcn20_pipe_control_lock(dc, top_pipe_to_program, false);
top_pipe_to_program 1261 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c 	if (num_planes > 0 && top_pipe_to_program &&
top_pipe_to_program 1264 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c 				top_pipe_to_program->plane_res.hubp->funcs->hubp_is_flip_pending(top_pipe_to_program->plane_res.hubp)) {