tmdsck             79 drivers/gpu/drm/sti/sti_hdmi_tx3g4c28phy.c 	u32 val, tmdsck, idf, odf, pllctrl = 0;
tmdsck            102 drivers/gpu/drm/sti/sti_hdmi_tx3g4c28phy.c 	tmdsck = ckpxpll;
tmdsck            105 drivers/gpu/drm/sti/sti_hdmi_tx3g4c28phy.c 	if (tmdsck > 340000000) {
tmdsck            106 drivers/gpu/drm/sti/sti_hdmi_tx3g4c28phy.c 		DRM_ERROR("output TMDS clock (%d) out of range\n", tmdsck);
tmdsck            138 drivers/gpu/drm/sti/sti_hdmi_tx3g4c28phy.c 	if (tmdsck > 165000000)
tmdsck            147 drivers/gpu/drm/sti/sti_hdmi_tx3g4c28phy.c 		if ((hdmiphy_config[i].min_tmds_freq <= tmdsck) &&
tmdsck            148 drivers/gpu/drm/sti/sti_hdmi_tx3g4c28phy.c 		    (hdmiphy_config[i].max_tmds_freq >= tmdsck)) {