THM_BASE           54 drivers/gpu/drm/amd/amdgpu/arct_reg_init.c 		adev->reg_offset[THM_HWIP][i] = (uint32_t *)(&(THM_BASE.instance[i]));
THM_BASE           49 drivers/gpu/drm/amd/amdgpu/navi10_reg_init.c 		adev->reg_offset[THM_HWIP][i] = (uint32_t *)(&(THM_BASE.instance[i]));
THM_BASE           49 drivers/gpu/drm/amd/amdgpu/navi12_reg_init.c 		adev->reg_offset[THM_HWIP][i] = (uint32_t *)(&(THM_BASE.instance[i]));
THM_BASE           49 drivers/gpu/drm/amd/amdgpu/navi14_reg_init.c 		adev->reg_offset[THM_HWIP][i] = (uint32_t *)(&(THM_BASE.instance[i]));
THM_BASE           53 drivers/gpu/drm/amd/amdgpu/vega10_reg_init.c 		adev->reg_offset[THM_HWIP][i] = (uint32_t *)(&(THM_BASE.instance[i]));
THM_BASE           51 drivers/gpu/drm/amd/amdgpu/vega20_reg_init.c 		adev->reg_offset[THM_HWIP][i] = (uint32_t *)(&(THM_BASE.instance[i]));
THM_BASE          205 drivers/gpu/drm/amd/include/arct_ip_offset.h static const struct IP_BASE THM_BASE            ={ { { { 0x00016600, 0, 0, 0, 0, 0 } },
THM_BASE          121 drivers/gpu/drm/amd/include/navi10_ip_offset.h static const struct IP_BASE THM_BASE            ={ { { { 0x00016600, 0, 0, 0, 0, 0 } },
THM_BASE          165 drivers/gpu/drm/amd/include/navi12_ip_offset.h static const struct IP_BASE THM_BASE ={ { { { 0x00016600, 0x02400C00, 0, 0, 0 } },
THM_BASE          165 drivers/gpu/drm/amd/include/navi14_ip_offset.h static const struct IP_BASE THM_BASE ={ { { { 0x00016600, 0x02400C00, 0, 0, 0 } },
THM_BASE          200 drivers/gpu/drm/amd/include/renoir_ip_offset.h static const struct IP_BASE THM_BASE ={ { { { 0x00016600, 0x02400C00, 0, 0, 0 } },
THM_BASE          188 drivers/gpu/drm/amd/include/vega10_ip_offset.h static const struct IP_BASE THM_BASE			= { { { { 0x00016600, 0, 0, 0, 0 } },
THM_BASE          129 drivers/gpu/drm/amd/include/vega20_ip_offset.h static const struct IP_BASE THM_BASE            ={ { { { 0x00016600, 0, 0, 0, 0, 0 } },