THM 1104 drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c uint32_t reg_value = RREG32_SOC15(THM, 0, mmTHM_TCON_CUR_TMP); THM 44 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_baco.c {CMD_WAITFOR, SOC15_REG_ENTRY(THM, 0, mmTHM_BACO_CNTL), THM_BACO_CNTL__SOC_DOMAIN_IDLE_MASK, THM_BACO_CNTL__SOC_DOMAIN_IDLE__SHIFT, 0xffffffff, 0x80000000}, THM 48 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_baco.c {CMD_READMODIFYWRITE, SOC15_REG_ENTRY(THM, 0, mmTHM_BACO_CNTL), THM_BACO_CNTL__BACO_SOC_VDCI_RESET_MASK, THM_BACO_CNTL__BACO_SOC_VDCI_RESET__SHIFT, 0, 1}, THM 49 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_baco.c {CMD_READMODIFYWRITE, SOC15_REG_ENTRY(THM, 0, mmTHM_BACO_CNTL), THM_BACO_CNTL__BACO_SMNCLK_MUX_MASK, THM_BACO_CNTL__BACO_SMNCLK_MUX__SHIFT,0, 1}, THM 50 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_baco.c {CMD_READMODIFYWRITE, SOC15_REG_ENTRY(THM, 0, mmTHM_BACO_CNTL), THM_BACO_CNTL__BACO_ISO_EN_MASK, THM_BACO_CNTL__BACO_ISO_EN__SHIFT, 0, 1}, THM 51 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_baco.c {CMD_READMODIFYWRITE, SOC15_REG_ENTRY(THM, 0, mmTHM_BACO_CNTL), THM_BACO_CNTL__BACO_AEB_ISO_EN_MASK, THM_BACO_CNTL__BACO_AEB_ISO_EN__SHIFT,0, 1}, THM 52 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_baco.c {CMD_READMODIFYWRITE, SOC15_REG_ENTRY(THM, 0, mmTHM_BACO_CNTL), THM_BACO_CNTL__BACO_ANA_ISO_EN_MASK, THM_BACO_CNTL__BACO_ANA_ISO_EN__SHIFT, 0, 1}, THM 53 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_baco.c {CMD_READMODIFYWRITE, SOC15_REG_ENTRY(THM, 0, mmTHM_BACO_CNTL), THM_BACO_CNTL__BACO_SOC_REFCLK_OFF_MASK, THM_BACO_CNTL__BACO_SOC_REFCLK_OFF__SHIFT, 0, 1}, THM 56 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_baco.c {CMD_READMODIFYWRITE, SOC15_REG_ENTRY(THM, 0, mmTHM_BACO_CNTL), THM_BACO_CNTL__BACO_RESET_EN_MASK, THM_BACO_CNTL__BACO_RESET_EN__SHIFT, 0, 1}, THM 57 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_baco.c {CMD_READMODIFYWRITE, SOC15_REG_ENTRY(THM, 0, mmTHM_BACO_CNTL), THM_BACO_CNTL__BACO_PWROKRAW_CNTL_MASK, THM_BACO_CNTL__BACO_PWROKRAW_CNTL__SHIFT, 0, 0}, THM 65 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_baco.c {CMD_READMODIFYWRITE, SOC15_REG_ENTRY(THM, 0, mmTHM_BACO_CNTL), THM_BACO_CNTL__BACO_SOC_REFCLK_OFF_MASK, THM_BACO_CNTL__BACO_SOC_REFCLK_OFF__SHIFT, 0,0}, THM 66 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_baco.c {CMD_READMODIFYWRITE, SOC15_REG_ENTRY(THM, 0, mmTHM_BACO_CNTL), THM_BACO_CNTL__BACO_ANA_ISO_EN_MASK, THM_BACO_CNTL__BACO_ANA_ISO_EN__SHIFT, 0, 0}, THM 67 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_baco.c {CMD_READMODIFYWRITE, SOC15_REG_ENTRY(THM, 0, mmTHM_BACO_CNTL), THM_BACO_CNTL__BACO_AEB_ISO_EN_MASK, THM_BACO_CNTL__BACO_AEB_ISO_EN__SHIFT,0, 0}, THM 68 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_baco.c {CMD_READMODIFYWRITE, SOC15_REG_ENTRY(THM, 0, mmTHM_BACO_CNTL), THM_BACO_CNTL__BACO_ISO_EN_MASK, THM_BACO_CNTL__BACO_ISO_EN__SHIFT, 0, 0}, THM 69 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_baco.c {CMD_READMODIFYWRITE, SOC15_REG_ENTRY(THM, 0, mmTHM_BACO_CNTL), THM_BACO_CNTL__BACO_PWROKRAW_CNTL_MASK, THM_BACO_CNTL__BACO_PWROKRAW_CNTL__SHIFT, 0, 1}, THM 70 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_baco.c {CMD_READMODIFYWRITE, SOC15_REG_ENTRY(THM, 0, mmTHM_BACO_CNTL), THM_BACO_CNTL__BACO_SMNCLK_MUX_MASK, THM_BACO_CNTL__BACO_SMNCLK_MUX__SHIFT, 0, 0}, THM 71 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_baco.c {CMD_READMODIFYWRITE, SOC15_REG_ENTRY(THM, 0, mmTHM_BACO_CNTL), THM_BACO_CNTL__BACO_SOC_VDCI_RESET_MASK, THM_BACO_CNTL__BACO_SOC_VDCI_RESET__SHIFT, 0, 0}, THM 72 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_baco.c {CMD_READMODIFYWRITE, SOC15_REG_ENTRY(THM, 0, mmTHM_BACO_CNTL), THM_BACO_CNTL__BACO_EXIT_MASK, THM_BACO_CNTL__BACO_EXIT__SHIFT, 0, 1}, THM 73 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_baco.c {CMD_READMODIFYWRITE, SOC15_REG_ENTRY(THM, 0, mmTHM_BACO_CNTL), THM_BACO_CNTL__BACO_RESET_EN_MASK, THM_BACO_CNTL__BACO_RESET_EN__SHIFT, 0, 0}, THM 74 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_baco.c {CMD_WAITFOR, SOC15_REG_ENTRY(THM, 0, mmTHM_BACO_CNTL), THM_BACO_CNTL__BACO_EXIT_MASK, 0, 0xffffffff, 0}, THM 75 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_baco.c {CMD_READMODIFYWRITE, SOC15_REG_ENTRY(THM, 0, mmTHM_BACO_CNTL), THM_BACO_CNTL__BACO_SB_AXI_FENCE_MASK, THM_BACO_CNTL__BACO_SB_AXI_FENCE__SHIFT, 0, 0}, THM 106 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_thermal.c REG_GET_FIELD(RREG32_SOC15(THM, 0, mmCG_TACH_STATUS), THM 134 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_thermal.c REG_GET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL2), THM 137 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_thermal.c REG_GET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL2), THM 142 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_thermal.c WREG32_SOC15(THM, 0, mmCG_FDO_CTRL2, THM 143 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_thermal.c REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL2), THM 145 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_thermal.c WREG32_SOC15(THM, 0, mmCG_FDO_CTRL2, THM 146 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_thermal.c REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL2), THM 162 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_thermal.c WREG32_SOC15(THM, 0, mmCG_FDO_CTRL2, THM 163 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_thermal.c REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL2), THM 166 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_thermal.c WREG32_SOC15(THM, 0, mmCG_FDO_CTRL2, THM 167 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_thermal.c REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL2), THM 268 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_thermal.c duty100 = REG_GET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL1), THM 278 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_thermal.c WREG32_SOC15(THM, 0, mmCG_FDO_CTRL0, THM 279 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_thermal.c REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL0), THM 326 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_thermal.c WREG32_SOC15(THM, 0, mmCG_TACH_CTRL, THM 327 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_thermal.c REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_TACH_CTRL), THM 344 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_thermal.c temp = RREG32_SOC15(THM, 0, mmCG_MULT_THERMAL_STATUS); THM 382 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_thermal.c val = RREG32_SOC15(THM, 0, mmTHM_THERMAL_INT_CTRL); THM 392 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_thermal.c WREG32_SOC15(THM, 0, mmTHM_THERMAL_INT_CTRL, val); THM 407 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_thermal.c WREG32_SOC15(THM, 0, mmCG_TACH_CTRL, THM 408 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_thermal.c REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_TACH_CTRL), THM 413 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_thermal.c WREG32_SOC15(THM, 0, mmCG_FDO_CTRL2, THM 414 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_thermal.c REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL2), THM 447 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_thermal.c WREG32_SOC15(THM, 0, mmTHM_THERMAL_INT_ENA, val); THM 474 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_thermal.c WREG32_SOC15(THM, 0, mmTHM_THERMAL_INT_ENA, 0); THM 151 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_thermal.c temp = RREG32_SOC15(THM, 0, mmCG_MULT_THERMAL_STATUS); THM 188 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_thermal.c val = RREG32_SOC15(THM, 0, mmTHM_THERMAL_INT_CTRL); THM 196 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_thermal.c WREG32_SOC15(THM, 0, mmTHM_THERMAL_INT_CTRL, val); THM 215 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_thermal.c WREG32_SOC15(THM, 0, mmTHM_THERMAL_INT_ENA, val); THM 228 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_thermal.c WREG32_SOC15(THM, 0, mmTHM_THERMAL_INT_ENA, 0); THM 89 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_baco.c data = RREG32_SOC15(THM, 0, mmTHM_BACO_CNTL); THM 91 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_baco.c WREG32_SOC15(THM, 0, mmTHM_BACO_CNTL, data); THM 94 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_thermal.c WREG32_SOC15(THM, 0, mmCG_FDO_CTRL2, THM 95 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_thermal.c REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL2), THM 97 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_thermal.c WREG32_SOC15(THM, 0, mmCG_FDO_CTRL2, THM 98 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_thermal.c REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL2), THM 150 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_thermal.c duty100 = REG_GET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL1), THM 160 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_thermal.c WREG32_SOC15(THM, 0, mmCG_FDO_CTRL0, THM 161 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_thermal.c REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL0), THM 203 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_thermal.c WREG32_SOC15(THM, 0, mmCG_TACH_CTRL, THM 204 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_thermal.c REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_TACH_CTRL), THM 221 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_thermal.c temp = RREG32_SOC15(THM, 0, mmCG_MULT_THERMAL_STATUS); THM 258 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_thermal.c val = RREG32_SOC15(THM, 0, mmTHM_THERMAL_INT_CTRL); THM 266 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_thermal.c WREG32_SOC15(THM, 0, mmTHM_THERMAL_INT_CTRL, val); THM 285 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_thermal.c WREG32_SOC15(THM, 0, mmTHM_THERMAL_INT_ENA, val); THM 298 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_thermal.c WREG32_SOC15(THM, 0, mmTHM_THERMAL_INT_ENA, 0); THM 1149 drivers/gpu/drm/amd/powerplay/smu_v11_0.c val = RREG32_SOC15(THM, 0, mmTHM_THERMAL_INT_CTRL); THM 1158 drivers/gpu/drm/amd/powerplay/smu_v11_0.c WREG32_SOC15(THM, 0, mmTHM_THERMAL_INT_CTRL, val); THM 1172 drivers/gpu/drm/amd/powerplay/smu_v11_0.c WREG32_SOC15(THM, 0, mmTHM_THERMAL_INT_ENA, val); THM 1412 drivers/gpu/drm/amd/powerplay/smu_v11_0.c WREG32_SOC15(THM, 0, mmCG_FDO_CTRL2, THM 1413 drivers/gpu/drm/amd/powerplay/smu_v11_0.c REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL2), THM 1415 drivers/gpu/drm/amd/powerplay/smu_v11_0.c WREG32_SOC15(THM, 0, mmCG_FDO_CTRL2, THM 1416 drivers/gpu/drm/amd/powerplay/smu_v11_0.c REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL2), THM 1435 drivers/gpu/drm/amd/powerplay/smu_v11_0.c duty100 = REG_GET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL1), THM 1444 drivers/gpu/drm/amd/powerplay/smu_v11_0.c WREG32_SOC15(THM, 0, mmCG_FDO_CTRL0, THM 1445 drivers/gpu/drm/amd/powerplay/smu_v11_0.c REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL0), THM 1496 drivers/gpu/drm/amd/powerplay/smu_v11_0.c WREG32_SOC15(THM, 0, mmCG_TACH_CTRL, THM 1497 drivers/gpu/drm/amd/powerplay/smu_v11_0.c REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_TACH_CTRL), THM 2994 drivers/gpu/drm/amd/powerplay/vega20_ppt.c temp = RREG32_SOC15(THM, 0, mmCG_MULT_THERMAL_STATUS);