timing_base        96 drivers/gpu/drm/exynos/exynos_drm_fimd.c 	unsigned int timing_base;
timing_base       115 drivers/gpu/drm/exynos/exynos_drm_fimd.c 	.timing_base = 0x0,
timing_base       121 drivers/gpu/drm/exynos/exynos_drm_fimd.c 	.timing_base = 0x0,
timing_base       127 drivers/gpu/drm/exynos/exynos_drm_fimd.c 	.timing_base = 0x20000,
timing_base       135 drivers/gpu/drm/exynos/exynos_drm_fimd.c 	.timing_base = 0x0,
timing_base       144 drivers/gpu/drm/exynos/exynos_drm_fimd.c 	.timing_base = 0x20000,
timing_base       155 drivers/gpu/drm/exynos/exynos_drm_fimd.c 	.timing_base = 0x20000,
timing_base       436 drivers/gpu/drm/exynos/exynos_drm_fimd.c 	void __iomem *timing_base = ctx->regs + ctx->driver_data->timing_base;
timing_base       438 drivers/gpu/drm/exynos/exynos_drm_fimd.c 	u32 val = readl(timing_base + TRIGCON);
timing_base       451 drivers/gpu/drm/exynos/exynos_drm_fimd.c 	writel(val, timing_base + TRIGCON);
timing_base       459 drivers/gpu/drm/exynos/exynos_drm_fimd.c 	void *timing_base = ctx->regs + driver_data->timing_base;
timing_base       471 drivers/gpu/drm/exynos/exynos_drm_fimd.c 		writel(val, timing_base + I80IFCONFAx(0));
timing_base       474 drivers/gpu/drm/exynos/exynos_drm_fimd.c 		writel(0, timing_base + I80IFCONFBx(0));
timing_base       496 drivers/gpu/drm/exynos/exynos_drm_fimd.c 		writel(vidcon1, ctx->regs + driver_data->timing_base + VIDCON1);
timing_base       506 drivers/gpu/drm/exynos/exynos_drm_fimd.c 		writel(val, ctx->regs + driver_data->timing_base + VIDTCON0);
timing_base       516 drivers/gpu/drm/exynos/exynos_drm_fimd.c 		writel(val, ctx->regs + driver_data->timing_base + VIDTCON1);
timing_base       520 drivers/gpu/drm/exynos/exynos_drm_fimd.c 		writel(ctx->vidout_con, timing_base + VIDOUT_CON);
timing_base       550 drivers/gpu/drm/exynos/exynos_drm_fimd.c 	writel(val, ctx->regs + driver_data->timing_base + VIDTCON2);
timing_base       946 drivers/gpu/drm/exynos/exynos_drm_fimd.c 	void *timing_base = ctx->regs + driver_data->timing_base;
timing_base       959 drivers/gpu/drm/exynos/exynos_drm_fimd.c 	reg = readl(timing_base + TRIGCON);
timing_base       961 drivers/gpu/drm/exynos/exynos_drm_fimd.c 	writel(reg, timing_base + TRIGCON);