timer_reg_base     35 arch/mips/loongson32/common/time.c static void __iomem *timer_reg_base;
timer_reg_base     40 arch/mips/loongson32/common/time.c 	__raw_writel(period, timer_reg_base + PWM_HRC);
timer_reg_base     41 arch/mips/loongson32/common/time.c 	__raw_writel(period, timer_reg_base + PWM_LRC);
timer_reg_base     46 arch/mips/loongson32/common/time.c 	__raw_writel(0x0, timer_reg_base + PWM_CNT);
timer_reg_base     47 arch/mips/loongson32/common/time.c 	__raw_writel(INT_EN | CNT_EN, timer_reg_base + PWM_CTRL);
timer_reg_base     52 arch/mips/loongson32/common/time.c 	timer_reg_base = ioremap_nocache(LS1X_TIMER_BASE, SZ_16);
timer_reg_base     53 arch/mips/loongson32/common/time.c 	if (!timer_reg_base)
timer_reg_base     86 arch/mips/loongson32/common/time.c 	count = __raw_readl(timer_reg_base + PWM_CNT);
timer_reg_base    131 arch/mips/loongson32/common/time.c 	__raw_writel(INT_EN | CNT_EN, timer_reg_base + PWM_CTRL);
timer_reg_base    140 arch/mips/loongson32/common/time.c 	__raw_writel(INT_EN | CNT_EN, timer_reg_base + PWM_CTRL);
timer_reg_base    149 arch/mips/loongson32/common/time.c 	__raw_writel(__raw_readl(timer_reg_base + PWM_CTRL) & ~CNT_EN,
timer_reg_base    150 arch/mips/loongson32/common/time.c 		     timer_reg_base + PWM_CTRL);
timer_reg_base     52 drivers/clocksource/timer-tegra.c static void __iomem *timer_reg_base;
timer_reg_base    113 drivers/clocksource/timer-tegra.c 	writel_relaxed(usec_config, timer_reg_base + TIMERUS_USEC_CFG);
timer_reg_base    169 drivers/clocksource/timer-tegra.c 	return readl_relaxed(timer_reg_base + TIMERUS_CNTR_1US);
timer_reg_base    175 drivers/clocksource/timer-tegra.c 	return readl_relaxed(timer_reg_base + TIMERUS_CNTR_1US);
timer_reg_base    262 drivers/clocksource/timer-tegra.c 	timer_reg_base = timer_of_base(to);
timer_reg_base    299 drivers/clocksource/timer-tegra.c 	writel_relaxed(usec_config, timer_reg_base + TIMERUS_USEC_CFG);
timer_reg_base    318 drivers/clocksource/timer-tegra.c 		cpu_to->of_base.base = timer_reg_base + base;
timer_reg_base    337 drivers/clocksource/timer-tegra.c 	ret = clocksource_mmio_init(timer_reg_base + TIMERUS_CNTR_1US,
timer_reg_base    366 drivers/clocksource/timer-tegra.c 	to->of_base.base = timer_reg_base;