timcon0           205 drivers/gpu/drm/mediatek/mtk_dsi.c 	u32 timcon0, timcon1, timcon2, timcon3;
timcon0           211 drivers/gpu/drm/mediatek/mtk_dsi.c 	timcon0 = T_LPX | T_HS_PREP << 8 | T_HS_ZERO << 16 | T_HS_TRAIL << 24;
timcon0           219 drivers/gpu/drm/mediatek/mtk_dsi.c 	writel(timcon0, dsi->regs + DSI_PHY_TIMECON0);