tiling_info 474 drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c amdgpu_bo_get_tiling_flags(robj, &args->data.tiling_info); tiling_info 484 drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c r = amdgpu_bo_set_tiling_flags(robj, args->data.tiling_info); tiling_info 2703 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c const union dc_tiling_info *tiling_info, tiling_info 2734 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c input.swizzle_mode = tiling_info->gfx9.swizzle; tiling_info 2768 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c union dc_tiling_info *tiling_info, tiling_info 2777 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c memset(tiling_info, 0, sizeof(*tiling_info)); tiling_info 2834 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c tiling_info->gfx8.num_banks = num_banks; tiling_info 2835 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c tiling_info->gfx8.array_mode = tiling_info 2837 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c tiling_info->gfx8.tile_split = tile_split; tiling_info 2838 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c tiling_info->gfx8.bank_width = bankw; tiling_info 2839 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c tiling_info->gfx8.bank_height = bankh; tiling_info 2840 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c tiling_info->gfx8.tile_aspect = mtaspect; tiling_info 2841 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c tiling_info->gfx8.tile_mode = tiling_info 2845 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c tiling_info->gfx8.array_mode = DC_ARRAY_1D_TILED_THIN1; tiling_info 2848 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c tiling_info->gfx8.pipe_config = tiling_info 2864 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c tiling_info->gfx9.num_pipes = tiling_info 2866 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c tiling_info->gfx9.num_banks = tiling_info 2868 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c tiling_info->gfx9.pipe_interleave = tiling_info 2870 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c tiling_info->gfx9.num_shader_engines = tiling_info 2872 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c tiling_info->gfx9.max_compressed_frags = tiling_info 2874 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c tiling_info->gfx9.num_rb_per_se = tiling_info 2876 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c tiling_info->gfx9.swizzle = tiling_info 2878 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c tiling_info->gfx9.shaderEnable = 1; tiling_info 2881 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c plane_size, tiling_info, tiling_info 3053 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c &plane_info->tiling_info, tiling_info 3109 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c dc_plane_state->tiling_info = plane_info.tiling_info; tiling_info 4562 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c tiling_flags, &plane_state->tiling_info, tiling_info 334 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c input->src.sw_mode = pipe->plane_state->tiling_info.gfx9.swizzle; tiling_info 343 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c input->src.macro_tile_size = swizzle_mode_to_macro_tile_size(pipe->plane_state->tiling_info.gfx9.swizzle); tiling_info 982 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c pipe->plane_state->tiling_info.gfx9.swizzle); tiling_info 1444 drivers/gpu/drm/amd/display/dc/core/dc.c if (memcmp(&u->plane_info->tiling_info, &u->surface->tiling_info, tiling_info 1452 drivers/gpu/drm/amd/display/dc/core/dc.c if (u->plane_info->tiling_info.gfx9.swizzle != DC_SW_LINEAR) { tiling_info 1723 drivers/gpu/drm/amd/display/dc/core/dc.c surface->tiling_info = tiling_info 1724 drivers/gpu/drm/amd/display/dc/core/dc.c srf_update->plane_info->tiling_info; tiling_info 142 drivers/gpu/drm/amd/display/dc/core/dc_debug.c plane_state->tiling_info.gfx8.num_banks, tiling_info 143 drivers/gpu/drm/amd/display/dc/core/dc_debug.c plane_state->tiling_info.gfx8.bank_width, tiling_info 144 drivers/gpu/drm/amd/display/dc/core/dc_debug.c plane_state->tiling_info.gfx8.bank_width_c, tiling_info 145 drivers/gpu/drm/amd/display/dc/core/dc_debug.c plane_state->tiling_info.gfx8.bank_height, tiling_info 146 drivers/gpu/drm/amd/display/dc/core/dc_debug.c plane_state->tiling_info.gfx8.bank_height_c, tiling_info 147 drivers/gpu/drm/amd/display/dc/core/dc_debug.c plane_state->tiling_info.gfx8.tile_aspect, tiling_info 148 drivers/gpu/drm/amd/display/dc/core/dc_debug.c plane_state->tiling_info.gfx8.tile_aspect_c, tiling_info 149 drivers/gpu/drm/amd/display/dc/core/dc_debug.c plane_state->tiling_info.gfx8.tile_split, tiling_info 150 drivers/gpu/drm/amd/display/dc/core/dc_debug.c plane_state->tiling_info.gfx8.tile_split_c, tiling_info 151 drivers/gpu/drm/amd/display/dc/core/dc_debug.c plane_state->tiling_info.gfx8.tile_mode, tiling_info 152 drivers/gpu/drm/amd/display/dc/core/dc_debug.c plane_state->tiling_info.gfx8.tile_mode_c); tiling_info 162 drivers/gpu/drm/amd/display/dc/core/dc_debug.c plane_state->tiling_info.gfx8.pipe_config, tiling_info 163 drivers/gpu/drm/amd/display/dc/core/dc_debug.c plane_state->tiling_info.gfx8.array_mode, tiling_info 171 drivers/gpu/drm/amd/display/dc/core/dc_debug.c plane_state->tiling_info.gfx9.swizzle); tiling_info 234 drivers/gpu/drm/amd/display/dc/core/dc_debug.c update->plane_info->tiling_info.gfx8.num_banks, tiling_info 235 drivers/gpu/drm/amd/display/dc/core/dc_debug.c update->plane_info->tiling_info.gfx8.bank_width, tiling_info 236 drivers/gpu/drm/amd/display/dc/core/dc_debug.c update->plane_info->tiling_info.gfx8.bank_width_c, tiling_info 237 drivers/gpu/drm/amd/display/dc/core/dc_debug.c update->plane_info->tiling_info.gfx8.bank_height, tiling_info 238 drivers/gpu/drm/amd/display/dc/core/dc_debug.c update->plane_info->tiling_info.gfx8.bank_height_c, tiling_info 239 drivers/gpu/drm/amd/display/dc/core/dc_debug.c update->plane_info->tiling_info.gfx8.tile_aspect, tiling_info 240 drivers/gpu/drm/amd/display/dc/core/dc_debug.c update->plane_info->tiling_info.gfx8.tile_aspect_c, tiling_info 241 drivers/gpu/drm/amd/display/dc/core/dc_debug.c update->plane_info->tiling_info.gfx8.tile_split, tiling_info 242 drivers/gpu/drm/amd/display/dc/core/dc_debug.c update->plane_info->tiling_info.gfx8.tile_split_c, tiling_info 243 drivers/gpu/drm/amd/display/dc/core/dc_debug.c update->plane_info->tiling_info.gfx8.tile_mode, tiling_info 244 drivers/gpu/drm/amd/display/dc/core/dc_debug.c update->plane_info->tiling_info.gfx8.tile_mode_c); tiling_info 251 drivers/gpu/drm/amd/display/dc/core/dc_debug.c update->plane_info->tiling_info.gfx8.pipe_config, tiling_info 252 drivers/gpu/drm/amd/display/dc/core/dc_debug.c update->plane_info->tiling_info.gfx8.array_mode, tiling_info 257 drivers/gpu/drm/amd/display/dc/core/dc_debug.c update->plane_info->tiling_info.gfx9.swizzle); tiling_info 2062 drivers/gpu/drm/amd/display/dc/core/dc_resource.c pipe_ctx->plane_state->tiling_info.gfx9.swizzle == DC_SW_UNKNOWN) { tiling_info 724 drivers/gpu/drm/amd/display/dc/dc.h union dc_tiling_info tiling_info; tiling_info 774 drivers/gpu/drm/amd/display/dc/dc.h union dc_tiling_info tiling_info; tiling_info 101 drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.c union dc_tiling_info *tiling_info) tiling_info 103 drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.c switch (tiling_info->gfx8.array_mode) { tiling_info 136 drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.c union dc_tiling_info *tiling_info, tiling_info 141 drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.c enum mi_tiling_format mi_tiling = get_mi_tiling(tiling_info); tiling_info 507 drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.c union dc_tiling_info *tiling_info, tiling_info 516 drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.c program_tiling(dce_mi, tiling_info); tiling_info 1845 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c if (pipe_ctx->plane_state->tiling_info.gfx8.array_mode == DC_ARRAY_LINEAR_GENERAL) tiling_info 2514 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c &plane_state->tiling_info, tiling_info 2526 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c &plane_state->tiling_info, tiling_info 526 drivers/gpu/drm/amd/display/dc/dce110/dce110_mem_input_v.c union dc_tiling_info *tiling_info, tiling_info 544 drivers/gpu/drm/amd/display/dc/dce110/dce110_mem_input_v.c switch (tiling_info->gfx8.array_mode) { tiling_info 566 drivers/gpu/drm/amd/display/dc/dce110/dce110_mem_input_v.c union dc_tiling_info *tiling_info, tiling_info 570 drivers/gpu/drm/amd/display/dc/dce110/dce110_mem_input_v.c const unsigned int *pte = get_dvmm_hw_setting(tiling_info, format, false); tiling_info 571 drivers/gpu/drm/amd/display/dc/dce110/dce110_mem_input_v.c const unsigned int *pte_chroma = get_dvmm_hw_setting(tiling_info, format, true); tiling_info 639 drivers/gpu/drm/amd/display/dc/dce110/dce110_mem_input_v.c union dc_tiling_info *tiling_info, tiling_info 648 drivers/gpu/drm/amd/display/dc/dce110/dce110_mem_input_v.c program_tiling(mem_input110, tiling_info, format); tiling_info 528 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c union dc_tiling_info *tiling_info, tiling_info 536 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c hubp1_program_tiling(hubp, tiling_info, format); tiling_info 663 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h union dc_tiling_info *tiling_info, tiling_info 2393 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c &plane_state->tiling_info, tiling_info 1211 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c plane_state->tiling_info.gfx9.swizzle = swizzle; tiling_info 519 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c union dc_tiling_info *tiling_info, tiling_info 529 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c hubp2_program_tiling(hubp2, tiling_info, format); tiling_info 310 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.h union dc_tiling_info *tiling_info, tiling_info 2130 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c swizzle_mode_to_macro_tile_size(pln->tiling_info.gfx9.swizzle); tiling_info 2131 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c swizzle_to_dml_params(pln->tiling_info.gfx9.swizzle, tiling_info 3000 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c plane_state->tiling_info.gfx9.swizzle = swizzle; tiling_info 97 drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h union dc_tiling_info *tiling_info, tiling_info 111 drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h union dc_tiling_info *tiling_info, tiling_info 141 drivers/gpu/drm/amd/display/dc/inc/hw/mem_input.h union dc_tiling_info *tiling_info, tiling_info 155 drivers/gpu/drm/amd/display/dc/inc/hw/mem_input.h union dc_tiling_info *tiling_info, tiling_info 368 include/uapi/drm/amdgpu_drm.h __u64 tiling_info;