tiling_flags 161 drivers/gpu/drm/amd/amdgpu/amdgpu_display.c u64 tiling_flags; tiling_flags 216 drivers/gpu/drm/amd/amdgpu/amdgpu_display.c amdgpu_bo_get_tiling_flags(new_abo, &tiling_flags); tiling_flags 129 drivers/gpu/drm/amd/amdgpu/amdgpu_fb.c u32 tiling_flags = 0, domain; tiling_flags 157 drivers/gpu/drm/amd/amdgpu/amdgpu_fb.c tiling_flags = AMDGPU_TILING_SET(ARRAY_MODE, GRPH_ARRAY_2D_TILED_THIN1); tiling_flags 163 drivers/gpu/drm/amd/amdgpu/amdgpu_fb.c if (tiling_flags) { tiling_flags 165 drivers/gpu/drm/amd/amdgpu/amdgpu_fb.c tiling_flags); tiling_flags 1137 drivers/gpu/drm/amd/amdgpu/amdgpu_object.c int amdgpu_bo_set_tiling_flags(struct amdgpu_bo *bo, u64 tiling_flags) tiling_flags 1142 drivers/gpu/drm/amd/amdgpu/amdgpu_object.c AMDGPU_TILING_GET(tiling_flags, TILE_SPLIT) > 6) tiling_flags 1145 drivers/gpu/drm/amd/amdgpu/amdgpu_object.c bo->tiling_flags = tiling_flags; tiling_flags 1157 drivers/gpu/drm/amd/amdgpu/amdgpu_object.c void amdgpu_bo_get_tiling_flags(struct amdgpu_bo *bo, u64 *tiling_flags) tiling_flags 1161 drivers/gpu/drm/amd/amdgpu/amdgpu_object.c if (tiling_flags) tiling_flags 1162 drivers/gpu/drm/amd/amdgpu/amdgpu_object.c *tiling_flags = bo->tiling_flags; tiling_flags 89 drivers/gpu/drm/amd/amdgpu/amdgpu_object.h u64 tiling_flags; tiling_flags 260 drivers/gpu/drm/amd/amdgpu/amdgpu_object.h int amdgpu_bo_set_tiling_flags(struct amdgpu_bo *bo, u64 tiling_flags); tiling_flags 261 drivers/gpu/drm/amd/amdgpu/amdgpu_object.h void amdgpu_bo_get_tiling_flags(struct amdgpu_bo *bo, u64 *tiling_flags); tiling_flags 1839 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c uint64_t fb_location, tiling_flags; tiling_flags 1877 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c amdgpu_bo_get_tiling_flags(abo, &tiling_flags); tiling_flags 1880 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c pipe_config = AMDGPU_TILING_GET(tiling_flags, PIPE_CONFIG); tiling_flags 1970 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == ARRAY_2D_TILED_THIN1) { tiling_flags 1973 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c bankw = AMDGPU_TILING_GET(tiling_flags, BANK_WIDTH); tiling_flags 1974 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c bankh = AMDGPU_TILING_GET(tiling_flags, BANK_HEIGHT); tiling_flags 1975 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c mtaspect = AMDGPU_TILING_GET(tiling_flags, MACRO_TILE_ASPECT); tiling_flags 1976 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c tile_split = AMDGPU_TILING_GET(tiling_flags, TILE_SPLIT); tiling_flags 1977 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c num_banks = AMDGPU_TILING_GET(tiling_flags, NUM_BANKS); tiling_flags 1990 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c } else if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == ARRAY_1D_TILED_THIN1) { tiling_flags 1881 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c uint64_t fb_location, tiling_flags; tiling_flags 1919 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c amdgpu_bo_get_tiling_flags(abo, &tiling_flags); tiling_flags 1922 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c pipe_config = AMDGPU_TILING_GET(tiling_flags, PIPE_CONFIG); tiling_flags 2012 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == ARRAY_2D_TILED_THIN1) { tiling_flags 2015 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c bankw = AMDGPU_TILING_GET(tiling_flags, BANK_WIDTH); tiling_flags 2016 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c bankh = AMDGPU_TILING_GET(tiling_flags, BANK_HEIGHT); tiling_flags 2017 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c mtaspect = AMDGPU_TILING_GET(tiling_flags, MACRO_TILE_ASPECT); tiling_flags 2018 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c tile_split = AMDGPU_TILING_GET(tiling_flags, TILE_SPLIT); tiling_flags 2019 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c num_banks = AMDGPU_TILING_GET(tiling_flags, NUM_BANKS); tiling_flags 2032 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c } else if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == ARRAY_1D_TILED_THIN1) { tiling_flags 1797 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c uint64_t fb_location, tiling_flags; tiling_flags 1834 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c amdgpu_bo_get_tiling_flags(abo, &tiling_flags); tiling_flags 1917 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == ARRAY_2D_TILED_THIN1) { tiling_flags 1920 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c bankw = AMDGPU_TILING_GET(tiling_flags, BANK_WIDTH); tiling_flags 1921 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c bankh = AMDGPU_TILING_GET(tiling_flags, BANK_HEIGHT); tiling_flags 1922 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c mtaspect = AMDGPU_TILING_GET(tiling_flags, MACRO_TILE_ASPECT); tiling_flags 1923 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c tile_split = AMDGPU_TILING_GET(tiling_flags, TILE_SPLIT); tiling_flags 1924 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c num_banks = AMDGPU_TILING_GET(tiling_flags, NUM_BANKS); tiling_flags 1932 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c } else if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == ARRAY_1D_TILED_THIN1) { tiling_flags 1936 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c pipe_config = AMDGPU_TILING_GET(tiling_flags, PIPE_CONFIG); tiling_flags 1768 drivers/gpu/drm/amd/amdgpu/dce_v8_0.c uint64_t fb_location, tiling_flags; tiling_flags 1806 drivers/gpu/drm/amd/amdgpu/dce_v8_0.c amdgpu_bo_get_tiling_flags(abo, &tiling_flags); tiling_flags 1809 drivers/gpu/drm/amd/amdgpu/dce_v8_0.c pipe_config = AMDGPU_TILING_GET(tiling_flags, PIPE_CONFIG); tiling_flags 1891 drivers/gpu/drm/amd/amdgpu/dce_v8_0.c if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == ARRAY_2D_TILED_THIN1) { tiling_flags 1894 drivers/gpu/drm/amd/amdgpu/dce_v8_0.c bankw = AMDGPU_TILING_GET(tiling_flags, BANK_WIDTH); tiling_flags 1895 drivers/gpu/drm/amd/amdgpu/dce_v8_0.c bankh = AMDGPU_TILING_GET(tiling_flags, BANK_HEIGHT); tiling_flags 1896 drivers/gpu/drm/amd/amdgpu/dce_v8_0.c mtaspect = AMDGPU_TILING_GET(tiling_flags, MACRO_TILE_ASPECT); tiling_flags 1897 drivers/gpu/drm/amd/amdgpu/dce_v8_0.c tile_split = AMDGPU_TILING_GET(tiling_flags, TILE_SPLIT); tiling_flags 1898 drivers/gpu/drm/amd/amdgpu/dce_v8_0.c num_banks = AMDGPU_TILING_GET(tiling_flags, NUM_BANKS); tiling_flags 1907 drivers/gpu/drm/amd/amdgpu/dce_v8_0.c } else if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == ARRAY_1D_TILED_THIN1) { tiling_flags 2670 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c uint64_t *tiling_flags) tiling_flags 2682 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c if (tiling_flags) tiling_flags 2683 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c amdgpu_bo_get_tiling_flags(rbo, tiling_flags); tiling_flags 2690 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c static inline uint64_t get_dcc_address(uint64_t address, uint64_t tiling_flags) tiling_flags 2692 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c uint32_t offset = AMDGPU_TILING_GET(tiling_flags, DCC_OFFSET_256B); tiling_flags 2767 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c const uint64_t tiling_flags, tiling_flags 2824 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == DC_ARRAY_2D_TILED_THIN1) { tiling_flags 2827 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c bankw = AMDGPU_TILING_GET(tiling_flags, BANK_WIDTH); tiling_flags 2828 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c bankh = AMDGPU_TILING_GET(tiling_flags, BANK_HEIGHT); tiling_flags 2829 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c mtaspect = AMDGPU_TILING_GET(tiling_flags, MACRO_TILE_ASPECT); tiling_flags 2830 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c tile_split = AMDGPU_TILING_GET(tiling_flags, TILE_SPLIT); tiling_flags 2831 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c num_banks = AMDGPU_TILING_GET(tiling_flags, NUM_BANKS); tiling_flags 2843 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c } else if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) tiling_flags 2849 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c AMDGPU_TILING_GET(tiling_flags, PIPE_CONFIG); tiling_flags 2877 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c AMDGPU_TILING_GET(tiling_flags, SWIZZLE_MODE); tiling_flags 2882 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c tiling_flags, dcc, address, tiling_flags 2973 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c const uint64_t tiling_flags, tiling_flags 3052 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c plane_info->rotation, tiling_flags, tiling_flags 3077 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c uint64_t tiling_flags; tiling_flags 3090 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c ret = get_fb_info(amdgpu_fb, &tiling_flags); tiling_flags 3095 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c ret = fill_dc_plane_info_and_addr(adev, plane_state, tiling_flags, tiling_flags 4497 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c uint64_t tiling_flags; tiling_flags 4547 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c amdgpu_bo_get_tiling_flags(rbo, &tiling_flags); tiling_flags 4562 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c tiling_flags, &plane_state->tiling_info, tiling_flags 5689 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c uint64_t tiling_flags; tiling_flags 5782 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c amdgpu_bo_get_tiling_flags(abo, &tiling_flags); tiling_flags 5787 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c dm->adev, new_plane_state, tiling_flags, tiling_flags 7125 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c uint64_t tiling_flags; tiling_flags 7171 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c ret = get_fb_info(amdgpu_fb, &tiling_flags); tiling_flags 7178 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c dm->adev, new_plane_state, tiling_flags, tiling_flags 1155 drivers/gpu/drm/radeon/atombios_crtc.c uint32_t fb_format, fb_pitch_pixels, tiling_flags; tiling_flags 1193 drivers/gpu/drm/radeon/atombios_crtc.c radeon_bo_get_tiling_flags(rbo, &tiling_flags, NULL); tiling_flags 1276 drivers/gpu/drm/radeon/atombios_crtc.c if (tiling_flags & RADEON_TILING_MACRO) { tiling_flags 1277 drivers/gpu/drm/radeon/atombios_crtc.c evergreen_tiling_fields(tiling_flags, &bankw, &bankh, &mtaspect, &tile_split); tiling_flags 1350 drivers/gpu/drm/radeon/atombios_crtc.c } else if (tiling_flags & RADEON_TILING_MICRO) tiling_flags 1477 drivers/gpu/drm/radeon/atombios_crtc.c uint32_t fb_format, fb_pitch_pixels, tiling_flags; tiling_flags 1513 drivers/gpu/drm/radeon/atombios_crtc.c radeon_bo_get_tiling_flags(rbo, &tiling_flags, NULL); tiling_flags 1589 drivers/gpu/drm/radeon/atombios_crtc.c if (tiling_flags & RADEON_TILING_MACRO) tiling_flags 1591 drivers/gpu/drm/radeon/atombios_crtc.c else if (tiling_flags & RADEON_TILING_MICRO) tiling_flags 1594 drivers/gpu/drm/radeon/atombios_crtc.c if (tiling_flags & RADEON_TILING_MACRO) tiling_flags 1597 drivers/gpu/drm/radeon/atombios_crtc.c if (tiling_flags & RADEON_TILING_MICRO) tiling_flags 1114 drivers/gpu/drm/radeon/evergreen.c void evergreen_tiling_fields(unsigned tiling_flags, unsigned *bankw, tiling_flags 1118 drivers/gpu/drm/radeon/evergreen.c *bankw = (tiling_flags >> RADEON_TILING_EG_BANKW_SHIFT) & RADEON_TILING_EG_BANKW_MASK; tiling_flags 1119 drivers/gpu/drm/radeon/evergreen.c *bankh = (tiling_flags >> RADEON_TILING_EG_BANKH_SHIFT) & RADEON_TILING_EG_BANKH_MASK; tiling_flags 1120 drivers/gpu/drm/radeon/evergreen.c *mtaspect = (tiling_flags >> RADEON_TILING_EG_MACRO_TILE_ASPECT_SHIFT) & RADEON_TILING_EG_MACRO_TILE_ASPECT_MASK; tiling_flags 1121 drivers/gpu/drm/radeon/evergreen.c *tile_split = (tiling_flags >> RADEON_TILING_EG_TILE_SPLIT_SHIFT) & RADEON_TILING_EG_TILE_SPLIT_MASK; tiling_flags 93 drivers/gpu/drm/radeon/evergreen_cs.c static u32 evergreen_cs_get_aray_mode(u32 tiling_flags) tiling_flags 95 drivers/gpu/drm/radeon/evergreen_cs.c if (tiling_flags & RADEON_TILING_MACRO) tiling_flags 97 drivers/gpu/drm/radeon/evergreen_cs.c else if (tiling_flags & RADEON_TILING_MICRO) tiling_flags 1180 drivers/gpu/drm/radeon/evergreen_cs.c ib[idx] |= Z_ARRAY_MODE(evergreen_cs_get_aray_mode(reloc->tiling_flags)); tiling_flags 1181 drivers/gpu/drm/radeon/evergreen_cs.c track->db_z_info |= Z_ARRAY_MODE(evergreen_cs_get_aray_mode(reloc->tiling_flags)); tiling_flags 1182 drivers/gpu/drm/radeon/evergreen_cs.c if (reloc->tiling_flags & RADEON_TILING_MACRO) { tiling_flags 1185 drivers/gpu/drm/radeon/evergreen_cs.c evergreen_tiling_fields(reloc->tiling_flags, tiling_flags 1366 drivers/gpu/drm/radeon/evergreen_cs.c ib[idx] |= CB_ARRAY_MODE(evergreen_cs_get_aray_mode(reloc->tiling_flags)); tiling_flags 1367 drivers/gpu/drm/radeon/evergreen_cs.c track->cb_color_info[tmp] |= CB_ARRAY_MODE(evergreen_cs_get_aray_mode(reloc->tiling_flags)); tiling_flags 1384 drivers/gpu/drm/radeon/evergreen_cs.c ib[idx] |= CB_ARRAY_MODE(evergreen_cs_get_aray_mode(reloc->tiling_flags)); tiling_flags 1385 drivers/gpu/drm/radeon/evergreen_cs.c track->cb_color_info[tmp] |= CB_ARRAY_MODE(evergreen_cs_get_aray_mode(reloc->tiling_flags)); tiling_flags 1446 drivers/gpu/drm/radeon/evergreen_cs.c if (reloc->tiling_flags & RADEON_TILING_MACRO) { tiling_flags 1449 drivers/gpu/drm/radeon/evergreen_cs.c evergreen_tiling_fields(reloc->tiling_flags, tiling_flags 1474 drivers/gpu/drm/radeon/evergreen_cs.c if (reloc->tiling_flags & RADEON_TILING_MACRO) { tiling_flags 1477 drivers/gpu/drm/radeon/evergreen_cs.c evergreen_tiling_fields(reloc->tiling_flags, tiling_flags 2362 drivers/gpu/drm/radeon/evergreen_cs.c TEX_ARRAY_MODE(evergreen_cs_get_aray_mode(reloc->tiling_flags)); tiling_flags 2363 drivers/gpu/drm/radeon/evergreen_cs.c if (reloc->tiling_flags & RADEON_TILING_MACRO) { tiling_flags 2366 drivers/gpu/drm/radeon/evergreen_cs.c evergreen_tiling_fields(reloc->tiling_flags, tiling_flags 1283 drivers/gpu/drm/radeon/r100.c if (reloc->tiling_flags & RADEON_TILING_MACRO) tiling_flags 1285 drivers/gpu/drm/radeon/r100.c if (reloc->tiling_flags & RADEON_TILING_MICRO) { tiling_flags 1625 drivers/gpu/drm/radeon/r100.c if (reloc->tiling_flags & RADEON_TILING_MACRO) tiling_flags 1627 drivers/gpu/drm/radeon/r100.c if (reloc->tiling_flags & RADEON_TILING_MICRO) tiling_flags 1706 drivers/gpu/drm/radeon/r100.c if (reloc->tiling_flags & RADEON_TILING_MACRO) tiling_flags 1708 drivers/gpu/drm/radeon/r100.c if (reloc->tiling_flags & RADEON_TILING_MICRO) tiling_flags 3094 drivers/gpu/drm/radeon/r100.c uint32_t tiling_flags, uint32_t pitch, tiling_flags 3101 drivers/gpu/drm/radeon/r100.c if ((tiling_flags & (RADEON_TILING_MACRO|RADEON_TILING_MICRO)) tiling_flags 3104 drivers/gpu/drm/radeon/r100.c if (tiling_flags & RADEON_TILING_MACRO) tiling_flags 3107 drivers/gpu/drm/radeon/r100.c if ((tiling_flags & (RADEON_TILING_MACRO|RADEON_TILING_MICRO)) tiling_flags 3111 drivers/gpu/drm/radeon/r100.c if (tiling_flags & (RADEON_TILING_MACRO)) tiling_flags 3113 drivers/gpu/drm/radeon/r100.c if (tiling_flags & RADEON_TILING_MICRO) tiling_flags 3116 drivers/gpu/drm/radeon/r100.c if (tiling_flags & RADEON_TILING_MACRO) tiling_flags 3118 drivers/gpu/drm/radeon/r100.c if (tiling_flags & RADEON_TILING_MICRO) tiling_flags 3122 drivers/gpu/drm/radeon/r100.c if (tiling_flags & RADEON_TILING_SWAP_16BIT) tiling_flags 3124 drivers/gpu/drm/radeon/r100.c if (tiling_flags & RADEON_TILING_SWAP_32BIT) tiling_flags 221 drivers/gpu/drm/radeon/r200.c if (reloc->tiling_flags & RADEON_TILING_MACRO) tiling_flags 223 drivers/gpu/drm/radeon/r200.c if (reloc->tiling_flags & RADEON_TILING_MICRO) tiling_flags 293 drivers/gpu/drm/radeon/r200.c if (reloc->tiling_flags & RADEON_TILING_MACRO) tiling_flags 295 drivers/gpu/drm/radeon/r200.c if (reloc->tiling_flags & RADEON_TILING_MICRO) tiling_flags 723 drivers/gpu/drm/radeon/r300.c if (reloc->tiling_flags & RADEON_TILING_MACRO) tiling_flags 725 drivers/gpu/drm/radeon/r300.c if (reloc->tiling_flags & RADEON_TILING_MICRO) tiling_flags 727 drivers/gpu/drm/radeon/r300.c else if (reloc->tiling_flags & RADEON_TILING_MICRO_SQUARE) tiling_flags 792 drivers/gpu/drm/radeon/r300.c if (reloc->tiling_flags & RADEON_TILING_MACRO) tiling_flags 794 drivers/gpu/drm/radeon/r300.c if (reloc->tiling_flags & RADEON_TILING_MICRO) tiling_flags 796 drivers/gpu/drm/radeon/r300.c else if (reloc->tiling_flags & RADEON_TILING_MICRO_SQUARE) tiling_flags 877 drivers/gpu/drm/radeon/r300.c if (reloc->tiling_flags & RADEON_TILING_MACRO) tiling_flags 879 drivers/gpu/drm/radeon/r300.c if (reloc->tiling_flags & RADEON_TILING_MICRO) tiling_flags 881 drivers/gpu/drm/radeon/r300.c else if (reloc->tiling_flags & RADEON_TILING_MICRO_SQUARE) tiling_flags 3028 drivers/gpu/drm/radeon/r600.c uint32_t tiling_flags, uint32_t pitch, tiling_flags 1044 drivers/gpu/drm/radeon/r600_cs.c if (reloc->tiling_flags & RADEON_TILING_MACRO) { tiling_flags 1143 drivers/gpu/drm/radeon/r600_cs.c if (reloc->tiling_flags & RADEON_TILING_MACRO) { tiling_flags 1146 drivers/gpu/drm/radeon/r600_cs.c } else if (reloc->tiling_flags & RADEON_TILING_MICRO) { tiling_flags 1474 drivers/gpu/drm/radeon/r600_cs.c u32 tiling_flags) tiling_flags 1496 drivers/gpu/drm/radeon/r600_cs.c if (tiling_flags & RADEON_TILING_MACRO) tiling_flags 1498 drivers/gpu/drm/radeon/r600_cs.c else if (tiling_flags & RADEON_TILING_MICRO) tiling_flags 1967 drivers/gpu/drm/radeon/r600_cs.c if (reloc->tiling_flags & RADEON_TILING_MACRO) tiling_flags 1969 drivers/gpu/drm/radeon/r600_cs.c else if (reloc->tiling_flags & RADEON_TILING_MICRO) tiling_flags 1985 drivers/gpu/drm/radeon/r600_cs.c reloc->tiling_flags); tiling_flags 352 drivers/gpu/drm/radeon/radeon.h extern void evergreen_tiling_fields(unsigned tiling_flags, unsigned *bankw, tiling_flags 466 drivers/gpu/drm/radeon/radeon.h uint32_t tiling_flags; tiling_flags 498 drivers/gpu/drm/radeon/radeon.h u32 tiling_flags; tiling_flags 1935 drivers/gpu/drm/radeon/radeon.h uint32_t tiling_flags, uint32_t pitch, tiling_flags 91 drivers/gpu/drm/radeon/radeon_asic.h uint32_t tiling_flags, uint32_t pitch, tiling_flags 339 drivers/gpu/drm/radeon/radeon_asic.h uint32_t tiling_flags, uint32_t pitch, tiling_flags 493 drivers/gpu/drm/radeon/radeon_display.c uint32_t tiling_flags, pitch_pixels; tiling_flags 539 drivers/gpu/drm/radeon/radeon_display.c radeon_bo_get_tiling_flags(new_rbo, &tiling_flags, NULL); tiling_flags 547 drivers/gpu/drm/radeon/radeon_display.c if (tiling_flags & RADEON_TILING_MACRO) { tiling_flags 134 drivers/gpu/drm/radeon/radeon_fb.c u32 tiling_flags = 0; tiling_flags 161 drivers/gpu/drm/radeon/radeon_fb.c tiling_flags = RADEON_TILING_MACRO; tiling_flags 166 drivers/gpu/drm/radeon/radeon_fb.c tiling_flags |= RADEON_TILING_SWAP_32BIT; tiling_flags 169 drivers/gpu/drm/radeon/radeon_fb.c tiling_flags |= RADEON_TILING_SWAP_16BIT; tiling_flags 175 drivers/gpu/drm/radeon/radeon_fb.c if (tiling_flags) { tiling_flags 177 drivers/gpu/drm/radeon/radeon_fb.c tiling_flags | RADEON_TILING_SURFACE, tiling_flags 512 drivers/gpu/drm/radeon/radeon_gem.c r = radeon_bo_set_tiling_flags(robj, args->tiling_flags, args->pitch); tiling_flags 533 drivers/gpu/drm/radeon/radeon_gem.c radeon_bo_get_tiling_flags(rbo, &args->tiling_flags, &args->pitch); tiling_flags 386 drivers/gpu/drm/radeon/radeon_legacy_crtc.c uint32_t tiling_flags; tiling_flags 464 drivers/gpu/drm/radeon/radeon_legacy_crtc.c radeon_bo_get_tiling_flags(rbo, &tiling_flags, NULL); tiling_flags 466 drivers/gpu/drm/radeon/radeon_legacy_crtc.c if (tiling_flags & RADEON_TILING_MICRO) tiling_flags 483 drivers/gpu/drm/radeon/radeon_legacy_crtc.c if (tiling_flags & RADEON_TILING_MACRO) { tiling_flags 499 drivers/gpu/drm/radeon/radeon_legacy_crtc.c if (tiling_flags & RADEON_TILING_MACRO) { tiling_flags 594 drivers/gpu/drm/radeon/radeon_object.c lobj->tiling_flags = bo->tiling_flags; tiling_flags 599 drivers/gpu/drm/radeon/radeon_object.c lobj->tiling_flags = lobj->robj->tiling_flags; tiling_flags 615 drivers/gpu/drm/radeon/radeon_object.c if (!bo->tiling_flags) tiling_flags 654 drivers/gpu/drm/radeon/radeon_object.c radeon_set_surface_reg(rdev, i, bo->tiling_flags, bo->pitch, tiling_flags 676 drivers/gpu/drm/radeon/radeon_object.c uint32_t tiling_flags, uint32_t pitch) tiling_flags 684 drivers/gpu/drm/radeon/radeon_object.c bankw = (tiling_flags >> RADEON_TILING_EG_BANKW_SHIFT) & RADEON_TILING_EG_BANKW_MASK; tiling_flags 685 drivers/gpu/drm/radeon/radeon_object.c bankh = (tiling_flags >> RADEON_TILING_EG_BANKH_SHIFT) & RADEON_TILING_EG_BANKH_MASK; tiling_flags 686 drivers/gpu/drm/radeon/radeon_object.c mtaspect = (tiling_flags >> RADEON_TILING_EG_MACRO_TILE_ASPECT_SHIFT) & RADEON_TILING_EG_MACRO_TILE_ASPECT_MASK; tiling_flags 687 drivers/gpu/drm/radeon/radeon_object.c tilesplit = (tiling_flags >> RADEON_TILING_EG_TILE_SPLIT_SHIFT) & RADEON_TILING_EG_TILE_SPLIT_MASK; tiling_flags 688 drivers/gpu/drm/radeon/radeon_object.c stilesplit = (tiling_flags >> RADEON_TILING_EG_STENCIL_TILE_SPLIT_SHIFT) & RADEON_TILING_EG_STENCIL_TILE_SPLIT_MASK; tiling_flags 729 drivers/gpu/drm/radeon/radeon_object.c bo->tiling_flags = tiling_flags; tiling_flags 736 drivers/gpu/drm/radeon/radeon_object.c uint32_t *tiling_flags, tiling_flags 741 drivers/gpu/drm/radeon/radeon_object.c if (tiling_flags) tiling_flags 742 drivers/gpu/drm/radeon/radeon_object.c *tiling_flags = bo->tiling_flags; tiling_flags 753 drivers/gpu/drm/radeon/radeon_object.c if (!(bo->tiling_flags & RADEON_TILING_SURFACE)) tiling_flags 147 drivers/gpu/drm/radeon/radeon_object.h u32 tiling_flags, u32 pitch); tiling_flags 149 drivers/gpu/drm/radeon/radeon_object.h u32 *tiling_flags, u32 *pitch); tiling_flags 146 drivers/gpu/drm/radeon/radeon_vm.c list[0].tiling_flags = 0; tiling_flags 158 drivers/gpu/drm/radeon/radeon_vm.c list[idx].tiling_flags = 0; tiling_flags 858 include/uapi/drm/radeon_drm.h __u32 tiling_flags; tiling_flags 864 include/uapi/drm/radeon_drm.h __u32 tiling_flags;