tiling_config    1992 drivers/gpu/drm/radeon/r600.c 	u32 tiling_config;
tiling_config    2087 drivers/gpu/drm/radeon/r600.c 	tiling_config = 0;
tiling_config    2091 drivers/gpu/drm/radeon/r600.c 		tiling_config |= PIPE_TILING(0);
tiling_config    2094 drivers/gpu/drm/radeon/r600.c 		tiling_config |= PIPE_TILING(1);
tiling_config    2097 drivers/gpu/drm/radeon/r600.c 		tiling_config |= PIPE_TILING(2);
tiling_config    2100 drivers/gpu/drm/radeon/r600.c 		tiling_config |= PIPE_TILING(3);
tiling_config    2107 drivers/gpu/drm/radeon/r600.c 	tiling_config |= BANK_TILING((ramcfg & NOOFBANK_MASK) >> NOOFBANK_SHIFT);
tiling_config    2108 drivers/gpu/drm/radeon/r600.c 	tiling_config |= GROUP_SIZE((ramcfg & BURSTLENGTH_MASK) >> BURSTLENGTH_SHIFT);
tiling_config    2112 drivers/gpu/drm/radeon/r600.c 		tiling_config |= ROW_TILING(3);
tiling_config    2113 drivers/gpu/drm/radeon/r600.c 		tiling_config |= SAMPLE_SPLIT(3);
tiling_config    2115 drivers/gpu/drm/radeon/r600.c 		tiling_config |= ROW_TILING(tmp);
tiling_config    2116 drivers/gpu/drm/radeon/r600.c 		tiling_config |= SAMPLE_SPLIT(tmp);
tiling_config    2118 drivers/gpu/drm/radeon/r600.c 	tiling_config |= BANK_SWAPS(1);
tiling_config    2134 drivers/gpu/drm/radeon/r600.c 	tmp = (tiling_config & PIPE_TILING__MASK) >> PIPE_TILING__SHIFT;
tiling_config    2137 drivers/gpu/drm/radeon/r600.c 	tiling_config |= tmp << 16;
tiling_config    2140 drivers/gpu/drm/radeon/r600.c 	rdev->config.r600.tile_config = tiling_config;
tiling_config    2141 drivers/gpu/drm/radeon/r600.c 	WREG32(GB_TILING_CONFIG, tiling_config);
tiling_config    2142 drivers/gpu/drm/radeon/r600.c 	WREG32(DCP_TILING_CONFIG, tiling_config & 0xffff);
tiling_config    2143 drivers/gpu/drm/radeon/r600.c 	WREG32(HDP_TILING_CONFIG, tiling_config & 0xffff);
tiling_config    2144 drivers/gpu/drm/radeon/r600.c 	WREG32(DMA_TILING_CONFIG, tiling_config & 0xffff);