tiling            325 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c 		unsigned int tiling,
tiling            330 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c 	bool surf_linear = (tiling == dm_sw_linear);
tiling            401 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c 			(enum dm_swizzle_mode)(tiling),
tiling            439 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c 	if (tiling != dm_sw_linear)
tiling            325 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c 		unsigned int tiling,
tiling            330 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c 	bool surf_linear = (tiling == dm_sw_linear);
tiling            401 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c 			(enum dm_swizzle_mode)(tiling),
tiling            439 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c 	if (tiling != dm_sw_linear)
tiling            313 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c 		unsigned int tiling,
tiling            319 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c 	bool surf_linear = (tiling == dm_sw_linear);
tiling            394 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c 			(enum dm_swizzle_mode) (tiling),
tiling            432 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c 	if (tiling != dm_sw_linear)
tiling            371 drivers/gpu/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c 		int tiling,
tiling            376 drivers/gpu/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c 	bool surf_linear = (tiling == dm_sw_linear);
tiling            427 drivers/gpu/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c 	if (tiling != dm_sw_linear)
tiling           3078 drivers/gpu/drm/i915/display/intel_display.c 	switch (plane_config->tiling) {
tiling           3083 drivers/gpu/drm/i915/display/intel_display.c 		obj->tiling_and_stride = fb->pitches[0] | plane_config->tiling;
tiling           3086 drivers/gpu/drm/i915/display/intel_display.c 		MISSING_CASE(plane_config->tiling);
tiling           3267 drivers/gpu/drm/i915/display/intel_display.c 	if (plane_config->tiling)
tiling           8622 drivers/gpu/drm/i915/display/intel_display.c 			plane_config->tiling = I915_TILING_X;
tiling           8642 drivers/gpu/drm/i915/display/intel_display.c 		if (plane_config->tiling)
tiling           9800 drivers/gpu/drm/i915/display/intel_display.c 	u32 val, base, offset, stride_mult, tiling, alpha;
tiling           9839 drivers/gpu/drm/i915/display/intel_display.c 	tiling = val & PLANE_CTL_TILED_MASK;
tiling           9840 drivers/gpu/drm/i915/display/intel_display.c 	switch (tiling) {
tiling           9845 drivers/gpu/drm/i915/display/intel_display.c 		plane_config->tiling = I915_TILING_X;
tiling           9849 drivers/gpu/drm/i915/display/intel_display.c 		plane_config->tiling = I915_TILING_Y;
tiling           9862 drivers/gpu/drm/i915/display/intel_display.c 		MISSING_CASE(tiling);
tiling           15599 drivers/gpu/drm/i915/display/intel_display.c 	unsigned int tiling, stride;
tiling           15608 drivers/gpu/drm/i915/display/intel_display.c 	tiling = i915_gem_object_get_tiling(obj);
tiling           15617 drivers/gpu/drm/i915/display/intel_display.c 		if (tiling != I915_TILING_NONE &&
tiling           15618 drivers/gpu/drm/i915/display/intel_display.c 		    tiling != intel_fb_modifier_to_tiling(mode_cmd->modifier[0])) {
tiling           15623 drivers/gpu/drm/i915/display/intel_display.c 		if (tiling == I915_TILING_X) {
tiling           15625 drivers/gpu/drm/i915/display/intel_display.c 		} else if (tiling == I915_TILING_Y) {
tiling           15648 drivers/gpu/drm/i915/display/intel_display.c 	    tiling != intel_fb_modifier_to_tiling(mode_cmd->modifier[0])) {
tiling           15667 drivers/gpu/drm/i915/display/intel_display.c 	if (tiling != I915_TILING_NONE && mode_cmd->pitches[0] != stride) {
tiling            579 drivers/gpu/drm/i915/display/intel_display_types.h 	unsigned int tiling;
tiling            192 drivers/gpu/drm/i915/gem/i915_gem_object.h i915_gem_tile_height(unsigned int tiling)
tiling            194 drivers/gpu/drm/i915/gem/i915_gem_object.h 	GEM_BUG_ON(!tiling);
tiling            195 drivers/gpu/drm/i915/gem/i915_gem_object.h 	return tiling == I915_TILING_Y ? 32 : 8;
tiling            212 drivers/gpu/drm/i915/gem/i915_gem_object.h 			       unsigned int tiling, unsigned int stride);
tiling             54 drivers/gpu/drm/i915/gem/i915_gem_tiling.c 			u32 size, unsigned int tiling, unsigned int stride)
tiling             60 drivers/gpu/drm/i915/gem/i915_gem_tiling.c 	if (tiling == I915_TILING_NONE)
tiling             66 drivers/gpu/drm/i915/gem/i915_gem_tiling.c 		stride *= i915_gem_tile_height(tiling);
tiling             94 drivers/gpu/drm/i915/gem/i915_gem_tiling.c 			     unsigned int tiling, unsigned int stride)
tiling            102 drivers/gpu/drm/i915/gem/i915_gem_tiling.c 	if (tiling == I915_TILING_NONE)
tiling            112 drivers/gpu/drm/i915/gem/i915_gem_tiling.c 	return i915_gem_fence_size(i915, size, tiling, stride);
tiling            118 drivers/gpu/drm/i915/gem/i915_gem_tiling.c 	       unsigned int tiling, unsigned int stride)
tiling            124 drivers/gpu/drm/i915/gem/i915_gem_tiling.c 	if (tiling == I915_TILING_NONE)
tiling            127 drivers/gpu/drm/i915/gem/i915_gem_tiling.c 	if (tiling > I915_TILING_LAST)
tiling            148 drivers/gpu/drm/i915/gem/i915_gem_tiling.c 	    (tiling == I915_TILING_Y && HAS_128_BYTE_Y_TILING(i915)))
tiling            204 drivers/gpu/drm/i915/gem/i915_gem_tiling.c 			   unsigned int tiling, unsigned int stride)
tiling            213 drivers/gpu/drm/i915/gem/i915_gem_tiling.c 	GEM_BUG_ON(!i915_tiling_ok(obj, tiling, stride));
tiling            214 drivers/gpu/drm/i915/gem/i915_gem_tiling.c 	GEM_BUG_ON(!stride ^ (tiling == I915_TILING_NONE));
tiling            217 drivers/gpu/drm/i915/gem/i915_gem_tiling.c 	if ((tiling | stride) == obj->tiling_and_stride)
tiling            236 drivers/gpu/drm/i915/gem/i915_gem_tiling.c 	err = i915_gem_object_fence_prepare(obj, tiling, stride);
tiling            254 drivers/gpu/drm/i915/gem/i915_gem_tiling.c 		if (tiling == I915_TILING_NONE) {
tiling            269 drivers/gpu/drm/i915/gem/i915_gem_tiling.c 			i915_gem_fence_size(i915, vma->size, tiling, stride);
tiling            272 drivers/gpu/drm/i915/gem/i915_gem_tiling.c 						 vma->size, tiling, stride);
tiling            278 drivers/gpu/drm/i915/gem/i915_gem_tiling.c 	obj->tiling_and_stride = tiling | stride;
tiling             20 drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c 	unsigned int tiling;
tiling             33 drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c 	if (tile->tiling == I915_TILING_NONE)
tiling             39 drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c 	if (tile->tiling == I915_TILING_X) {
tiling             89 drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c 			__func__, tile->tiling, tile->stride))
tiling             92 drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c 	err = i915_gem_object_set_tiling(obj, tile->tiling, tile->stride);
tiling             95 drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c 		       tile->tiling, tile->stride, err);
tiling             99 drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c 	GEM_BUG_ON(i915_gem_object_get_tiling(obj) != tile->tiling);
tiling            158 drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c 			       tile->tiling ? tile_row_pages(obj) : 0,
tiling            159 drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c 			       vma->fence ? vma->fence->id : -1, tile->tiling, tile->stride,
tiling            184 drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c 	int tiling;
tiling            220 drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c 		tile.tiling = I915_TILING_NONE;
tiling            227 drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c 	for (tiling = I915_TILING_X; tiling <= I915_TILING_Y; tiling++) {
tiling            241 drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c 		tile.tiling = tiling;
tiling            242 drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c 		switch (tiling) {
tiling            260 drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c 		} else if (tile.tiling == I915_TILING_Y &&
tiling           2405 drivers/gpu/drm/i915/i915_drv.h 			unsigned int tiling, unsigned int stride);
tiling           2407 drivers/gpu/drm/i915/i915_drv.h 			     unsigned int tiling, unsigned int stride);
tiling            126 drivers/gpu/drm/i915/i915_gem_fence_reg.c 		unsigned int tiling = i915_gem_object_get_tiling(vma->obj);
tiling            127 drivers/gpu/drm/i915/i915_gem_fence_reg.c 		bool is_y_tiled = tiling == I915_TILING_Y;
tiling            414 drivers/gpu/drm/tegra/dc.c 		unsigned long height = window->tiling.value;
tiling            416 drivers/gpu/drm/tegra/dc.c 		switch (window->tiling.mode) {
tiling            433 drivers/gpu/drm/tegra/dc.c 		switch (window->tiling.mode) {
tiling            605 drivers/gpu/drm/tegra/dc.c 	struct tegra_bo_tiling *tiling = &plane_state->tiling;
tiling            632 drivers/gpu/drm/tegra/dc.c 	err = tegra_fb_get_tiling(state->fb, tiling);
tiling            636 drivers/gpu/drm/tegra/dc.c 	if (tiling->mode == TEGRA_BO_TILING_MODE_BLOCK &&
tiling            713 drivers/gpu/drm/tegra/dc.c 	window.tiling = state->tiling;
tiling            143 drivers/gpu/drm/tegra/dc.h 	struct tegra_bo_tiling tiling;
tiling            800 drivers/gpu/drm/tegra/drm.c 	bo->tiling.mode = mode;
tiling            801 drivers/gpu/drm/tegra/drm.c 	bo->tiling.value = value;
tiling            822 drivers/gpu/drm/tegra/drm.c 	switch (bo->tiling.mode) {
tiling            835 drivers/gpu/drm/tegra/drm.c 		args->value = bo->tiling.value;
tiling            175 drivers/gpu/drm/tegra/drm.h 			struct tegra_bo_tiling *tiling);
tiling             43 drivers/gpu/drm/tegra/fb.c 			struct tegra_bo_tiling *tiling)
tiling             49 drivers/gpu/drm/tegra/fb.c 		tiling->mode = TEGRA_BO_TILING_MODE_PITCH;
tiling             50 drivers/gpu/drm/tegra/fb.c 		tiling->value = 0;
tiling             54 drivers/gpu/drm/tegra/fb.c 		tiling->mode = TEGRA_BO_TILING_MODE_TILED;
tiling             55 drivers/gpu/drm/tegra/fb.c 		tiling->value = 0;
tiling             59 drivers/gpu/drm/tegra/fb.c 		tiling->mode = TEGRA_BO_TILING_MODE_BLOCK;
tiling             60 drivers/gpu/drm/tegra/fb.c 		tiling->value = 0;
tiling             64 drivers/gpu/drm/tegra/fb.c 		tiling->mode = TEGRA_BO_TILING_MODE_BLOCK;
tiling             65 drivers/gpu/drm/tegra/fb.c 		tiling->value = 1;
tiling             69 drivers/gpu/drm/tegra/fb.c 		tiling->mode = TEGRA_BO_TILING_MODE_BLOCK;
tiling             70 drivers/gpu/drm/tegra/fb.c 		tiling->value = 2;
tiling             74 drivers/gpu/drm/tegra/fb.c 		tiling->mode = TEGRA_BO_TILING_MODE_BLOCK;
tiling             75 drivers/gpu/drm/tegra/fb.c 		tiling->value = 3;
tiling             79 drivers/gpu/drm/tegra/fb.c 		tiling->mode = TEGRA_BO_TILING_MODE_BLOCK;
tiling             80 drivers/gpu/drm/tegra/fb.c 		tiling->value = 4;
tiling             84 drivers/gpu/drm/tegra/fb.c 		tiling->mode = TEGRA_BO_TILING_MODE_BLOCK;
tiling             85 drivers/gpu/drm/tegra/fb.c 		tiling->value = 5;
tiling            295 drivers/gpu/drm/tegra/gem.c 		bo->tiling.mode = TEGRA_BO_TILING_MODE_TILED;
tiling             43 drivers/gpu/drm/tegra/gem.h 	struct tegra_bo_tiling tiling;
tiling            331 drivers/gpu/drm/tegra/hub.c 	struct tegra_bo_tiling *tiling = &plane_state->tiling;
tiling            345 drivers/gpu/drm/tegra/hub.c 	err = tegra_fb_get_tiling(state->fb, tiling);
tiling            349 drivers/gpu/drm/tegra/hub.c 	if (tiling->mode == TEGRA_BO_TILING_MODE_BLOCK &&
tiling            492 drivers/gpu/drm/tegra/hub.c 		unsigned long height = state->tiling.value;
tiling            495 drivers/gpu/drm/tegra/hub.c 		switch (state->tiling.mode) {
tiling             54 drivers/gpu/drm/tegra/plane.c 	copy->tiling = state->tiling;
tiling             42 drivers/gpu/drm/tegra/plane.h 	struct tegra_bo_tiling tiling;
tiling            598 drivers/gpu/drm/vc4/vc4_plane.c 	u32 tiling, src_y;
tiling            636 drivers/gpu/drm/vc4/vc4_plane.c 		tiling = SCALER_CTL0_TILING_LINEAR;
tiling            699 drivers/gpu/drm/vc4/vc4_plane.c 		tiling = SCALER_CTL0_TILING_256B_OR_T;
tiling            732 drivers/gpu/drm/vc4/vc4_plane.c 			tiling = SCALER_CTL0_TILING_64B;
tiling            736 drivers/gpu/drm/vc4/vc4_plane.c 			tiling = SCALER_CTL0_TILING_128B;
tiling            740 drivers/gpu/drm/vc4/vc4_plane.c 			tiling = SCALER_CTL0_TILING_256B_OR_T;
tiling            787 drivers/gpu/drm/vc4/vc4_plane.c 			VC4_SET_FIELD(tiling, SCALER_CTL0_TILING) |
tiling            440 drivers/gpu/drm/vc4/vc4_render_cl.c 	uint8_t tiling = VC4_GET_FIELD(surf->bits,
tiling            491 drivers/gpu/drm/vc4/vc4_render_cl.c 	if (tiling > VC4_TILING_FORMAT_LT) {
tiling            525 drivers/gpu/drm/vc4/vc4_render_cl.c 	if (!vc4_check_tex_size(exec, *obj, surf->offset, tiling,
tiling            539 drivers/gpu/drm/vc4/vc4_render_cl.c 	uint8_t tiling = VC4_GET_FIELD(surf->bits,
tiling            568 drivers/gpu/drm/vc4/vc4_render_cl.c 	if (tiling > VC4_TILING_FORMAT_LT) {
tiling            586 drivers/gpu/drm/vc4/vc4_render_cl.c 	if (!vc4_check_tex_size(exec, *obj, surf->offset, tiling,
tiling            919 drivers/staging/media/ipu3/ipu3-abi.h 	u32 tiling;
tiling           1025 drivers/staging/media/ipu3/ipu3-abi.h 	u32 tiling;		/* enum imgu_abi_osys_tiling */
tiling            315 drivers/staging/media/ipu3/ipu3-css-params.c 	unsigned int tiling;
tiling            428 drivers/staging/media/ipu3/ipu3-css-params.c 		unsigned int tiling = 0;
tiling            468 drivers/staging/media/ipu3/ipu3-css-params.c 						 &tiling);
tiling            474 drivers/staging/media/ipu3/ipu3-css-params.c 		frame_params[pin].tiling = tiling;
tiling           1003 drivers/staging/media/ipu3/ipu3-css-params.c 			fr_pr->tiling = frame_params[pin].tiling;
tiling           1086 drivers/staging/media/ipu3/ipu3-css-params.c 			if (frame_params[pin].tiling) {
tiling           1155 drivers/staging/media/ipu3/ipu3-css-params.c 			param->tiling = frame_params[pin].tiling;